[Intel-xe] [PATCH] drm/xe/pvc: Disable FPU Residue

Lucas De Marchi lucas.demarchi at intel.com
Tue Jul 18 15:04:25 UTC 2023


On Tue, Jul 18, 2023 at 12:16:12AM -0700, Niranjana Vishwanathapura wrote:
>To reduce the power consumption disable FPU residue on some specific
>devices if total EUs are 1024.
>
>v2: Minor cleanups (Matt)
>
>Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty at intel.com>
>Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
>---
> drivers/gpu/drm/xe/regs/xe_gt_regs.h |  1 +
> drivers/gpu/drm/xe/xe_gt_topology.c  |  3 ---
> drivers/gpu/drm/xe/xe_gt_types.h     |  3 +++
> drivers/gpu/drm/xe/xe_wa.c           | 34 ++++++++++++++++++++++++++++
> 4 files changed, 38 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>index d654f3311351..16405b16fddf 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>@@ -316,6 +316,7 @@
> #define   DIS_FIX_EOT1_FLUSH			REG_BIT(9)
>
> #define ROW_CHICKEN				XE_REG_MCR(0xe4f0, XE_REG_OPTION_MASKED)
>+#define   FPU_RESIDUE_DISABLE			REG_BIT(14)
> #define   UGM_BACKUP_MODE			REG_BIT(13)
> #define   MDQ_ARBITRATION_MODE			REG_BIT(12)
>
>diff --git a/drivers/gpu/drm/xe/xe_gt_topology.c b/drivers/gpu/drm/xe/xe_gt_topology.c
>index d4bbd0a835c2..a2da443160ab 100644
>--- a/drivers/gpu/drm/xe/xe_gt_topology.c
>+++ b/drivers/gpu/drm/xe/xe_gt_topology.c
>@@ -11,9 +11,6 @@
> #include "xe_gt.h"
> #include "xe_mmio.h"
>
>-#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
>-#define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS)
>-
> static void
> load_dss_mask(struct xe_gt *gt, xe_dss_mask_t mask, int numregs, ...)
> {
>diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
>index 78a9fe9f0bd3..76458169ec62 100644
>--- a/drivers/gpu/drm/xe/xe_gt_types.h
>+++ b/drivers/gpu/drm/xe/xe_gt_types.h
>@@ -25,7 +25,10 @@ enum xe_gt_type {
> };
>
> #define XE_MAX_DSS_FUSE_REGS	2
>+#define XE_MAX_DSS_FUSE_BITS (32 * XE_MAX_DSS_FUSE_REGS)
>+
> #define XE_MAX_EU_FUSE_REGS	1
>+#define XE_MAX_EU_FUSE_BITS (32 * XE_MAX_EU_FUSE_REGS)

this change and the one in xe_gt_topology.c should be a preparatory
patch on its own. Also, please match the style here: the value is
tab-aligned.

>
> typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)];
> typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)];
>diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>index 21087f7a4609..10496ed09119 100644
>--- a/drivers/gpu/drm/xe/xe_wa.c
>+++ b/drivers/gpu/drm/xe/xe_wa.c
>@@ -13,6 +13,7 @@
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_gt_regs.h"
> #include "regs/xe_regs.h"
>+#include "xe_device.h"
> #include "xe_device_types.h"
> #include "xe_force_wake.h"
> #include "xe_gt.h"
>@@ -256,6 +257,29 @@ static const struct xe_rtp_entry_sr gt_was[] = {
> 	{}
> };
>
>+static bool xe_wa_match_fpu_disable(const struct xe_gt *gt,
>+				    const struct xe_hw_engine *hwe)
>+{
>+	struct xe_device *xe = gt_to_xe(gt);
>+	u16 eu_count = 0;
>+	u8 gt_id;
>+
>+	/* FPU disabling is required for PVC 0x0BD6 device */
>+	if (xe->info.devid != 0x0BD6)
>+		return false;

this is very weird. Do we have a WA that matches per PCIID? That's not
how WAs are usuaally 

>+
>+	for_each_gt(gt, xe, gt_id) {
>+		u16 n_dss = bitmap_weight(gt->fuse_topo.c_dss_mask,
>+					  XE_MAX_DSS_FUSE_BITS);
>+		u16 n_eu = bitmap_weight(gt->fuse_topo.eu_mask_per_dss,
>+					 XE_MAX_EU_FUSE_BITS);
>+
>+		eu_count += n_dss * n_eu;
>+	}
>+
>+	return eu_count == 1024;
>+}
>+
> static const struct xe_rtp_entry_sr engine_was[] = {
> 	{ XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
> 	  XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
>@@ -518,6 +542,16 @@ static const struct xe_rtp_entry_sr engine_was[] = {
> 		       GRAPHICS_STEP(B0, C0)),
> 	  XE_RTP_ACTIONS(SET(CACHE_MODE_SS, DISABLE_ECC))
> 	},
>+	/*
>+	 * Not a workaround, but for tuning power.
>+	 * FPU residue disable will lower the power consumption.
>+	 */

So this is not the place. This table is specific for WAs.
We have xe_tunning.c for these tunings. Also please add the related
bspec in the commit message.

Lucas De Marchi

>+	{ XE_RTP_NAME("WaFPUResidueDisable"),
>+	  XE_RTP_RULES(PLATFORM(PVC),
>+		       FUNC(xe_rtp_match_first_render_or_compute),
>+		       FUNC(xe_wa_match_fpu_disable)),
>+	  XE_RTP_ACTIONS(SET(ROW_CHICKEN, FPU_RESIDUE_DISABLE)),
>+	},
>
> 	/* Xe_LPG */
> 	{ XE_RTP_NAME("14017856879"),
>-- 
>2.21.0.rc0.32.g243a4c7e27
>


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