[Intel-xe] ✗ CI.checkpatch: warning for series starting with [1/2] drm/xe/mtl: Map PPGTT as CPU:WC

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/xe/mtl: Map PPGTT as CPU:WC
URL   : https://patchwork.freedesktop.org/series/121148/
State : warning

== Summary ==

+ KERNEL=/kernel
+ git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt
Cloning into 'mt'...
warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/
+ git -C mt rev-list -n1 origin/master
c7d32770e3cd31d9fc134ce41f329b10aa33ee15
+ cd /kernel
+ git config --global --add safe.directory /kernel
+ git log -n1
commit 86ca568c0a00f932f1f49a11efd10ea2277a27a5
Author: Matt Roper <matthew.d.roper at intel.com>
Date:   Fri Jul 21 10:55:59 2023 -0700

    drm/xe: xe_engine_create_ioctl should check gt_count, not tile_count
    
    Platforms like MTL only have a single tile, but multiple GTs.
    Ensure XE_ENGINE_CREATE accepts engine creation on gt1 on such
    platforms.
    
    Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
+ /mt/dim checkpatch 786d2a4f30e168368b4d19d3e1d2f57d18ebecf8 drm-intel
f1b85f78b drm/xe/mtl: Map PPGTT as CPU:WC
-:11: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#11: 
   xe 0000:00:02.0: [drm:__xe_pt_bind_vma [xe]] Preparing bind, with range [1a0000...1a0fff) engine 0000000000000000.

total: 0 errors, 1 warnings, 0 checks, 45 lines checked
86ca568c0 drm/xe: xe_engine_create_ioctl should check gt_count, not tile_count