[Intel-xe] [PATCH] drm/xe: Fix MTL+ stolen memory mapping

[Matt Roper]

On Tue, Jul 25, 2023 at 09:43:44AM -0700, Lucas De Marchi wrote:
> Based on commit 8d8d062be6b9 ("drm/i915/mtl: Fix MTL stolen memory GGTT
> mapping"). For stolen on MTL and beyond, the address in the PTE is the
> offset from DSM base. While at it, update the comments explaining each
> part of the calculation.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
> 
> Untested as stolen in MTL is supposedly to be disabled. Need to find a
> proper way to test it.

It isn't actually disabled on Xe right now, so we can still test.

This patch by itself isn't quite enough, we also need:

	diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
	index b5bc9233c280..30e43663850c 100644
	--- a/drivers/gpu/drm/xe/xe_bo.c
	+++ b/drivers/gpu/drm/xe/xe_bo.c
	@@ -61,7 +61,8 @@ bool mem_type_is_vram(u32 mem_type)
	 
	 static bool resource_is_stolen_vram(struct xe_device *xe, struct ttm_resource *res)
	 {
	-       return res->mem_type == XE_PL_STOLEN && IS_DGFX(xe);
	+       return res->mem_type == XE_PL_STOLEN &&
	+               (IS_DGFX(xe) || GRAPHICS_VERx100(xe) >= 1270);
	 }
	 
	 static bool resource_is_vram(struct ttm_resource *res)

With that the framebuffer console starts working properly.

At some point we're also going to need to chop off the top of the stolen region
since the WOPCM area is reserved.  But that can be a future patch.


Matt

> 
>  drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c | 15 +++++++++++++--
>  1 file changed, 13 insertions(+), 2 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> index 21ecc734f10a..271b3fba4129 100644
> --- a/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> +++ b/drivers/gpu/drm/xe/xe_ttm_stolen_mgr.c
> @@ -94,11 +94,22 @@ static u32 detect_bar2_integrated(struct xe_device *xe, struct xe_ttm_stolen_mgr
>  
>  	ggc = xe_mmio_read32(xe_root_mmio_gt(xe), GGC);
>  
> -	/* check GGMS, should be fixed 0x3 (8MB) */
> +	/*
> +	 * Check GGMS: it should be fixed 0x3 (8MB), which corresponds to the
> +	 * GTT size
> +	 */
>  	if (drm_WARN_ON(&xe->drm, (ggc & GGMS_MASK) != GGMS_MASK))
>  		return 0;
>  
> -	mgr->stolen_base = mgr->io_base = pci_resource_start(pdev, 2) + SZ_8M;
> +	/*
> +	 * Graphics >= 1270 uses the offset to the GSMBASE as address in the
> +	 * PTEs, together with the DM flag being set. Previously there was no
> +	 * such flag so the address was the io_base.
> +	 *
> +	 * DSMBASE = GSMBASE + 8MB
> +	 */
> +	mgr->stolen_base = SZ_8M;
> +	mgr->io_base = pci_resource_start(pdev, 2) + mgr->stolen_base;
>  
>  	/* return valid GMS value, -EIO if invalid */
>  	gms = REG_FIELD_GET(GMS_MASK, ggc);
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation