[Intel-xe] [PATCH 1/2] drm/xe: Enable atomics on smem

Nirmoy Das nirmoy.das at intel.com
Wed Jul 26 07:42:59 UTC 2023


Atomics works on smem as well on supported platforms so
set AE PTE bit on smem as well if XE_VMA_ATOMIC_PTE_BIT
flag is set.

v2: Remove platform check(Lucas)

Signed-off-by: Nirmoy Das <nirmoy.das at intel.com>
---
 drivers/gpu/drm/xe/xe_pt.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
index d4660520ac2c..3bd6dd048305 100644
--- a/drivers/gpu/drm/xe/xe_pt.c
+++ b/drivers/gpu/drm/xe/xe_pt.c
@@ -768,10 +768,11 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
 	struct xe_pt *pt = xe_vma_vm(vma)->pt_root[tile->id];
 	int ret;
 
+	if (vma && vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT)
+		xe_walk.default_pte = XE_USM_PPGTT_PTE_AE;
+
 	if (is_vram) {
-		xe_walk.default_pte = XE_PPGTT_PTE_LM;
-		if (vma && vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT)
-			xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
+		xe_walk.default_pte |= XE_PPGTT_PTE_LM;
 		xe_walk.dma_offset = vram_region_gpu_offset(bo->ttm.resource);
 		xe_walk.cache = XE_CACHE_WB;
 	} else {
-- 
2.39.0



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