[Intel-xe] [PATCH v2 10/10] drm/xe: Sort xe_regs.h

[Matt Roper]

On Wed, Jul 26, 2023 at 09:07:08AM -0700, Lucas De Marchi wrote:
> Sort it by register address to make it easy to update when needed.
> 
> v2: Do not create exception for registers with same functionality.
> Always sort it.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_regs.h | 59 ++++++++++++++++---------------
>  1 file changed, 31 insertions(+), 28 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 315f6f8dadf3..ec45b1ba9db1 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -7,9 +7,6 @@
>  
>  #include "regs/xe_reg_defs.h"
>  
> -#define GU_CNTL					XE_REG(0x101010)
> -#define   LMEM_INIT				REG_BIT(7)
> -
>  #define RENDER_RING_BASE			0x02000
>  #define BSD_RING_BASE				0x1c0000
>  #define BSD2_RING_BASE				0x1c4000
> @@ -45,46 +42,52 @@
>  #define FF_THREAD_MODE				XE_REG(0x20a0)
>  #define   FF_TESSELATION_DOP_GATE_DISABLE	BIT(19)
>  
> -#define PVC_RP_STATE_CAP			XE_REG(0x281014)
> -#define MTL_RP_STATE_CAP			XE_REG(0x138000)
> -
> -#define MTL_MEDIAP_STATE_CAP			XE_REG(0x138020)
> -#define   MTL_RP0_CAP_MASK			REG_GENMASK(8, 0)
> -#define   MTL_RPN_CAP_MASK			REG_GENMASK(24, 16)
> -
> -#define MTL_GT_RPE_FREQUENCY			XE_REG(0x13800c)
> -#define MTL_MPE_FREQUENCY			XE_REG(0x13802c)
> -#define   MTL_RPE_MASK				REG_GENMASK(8, 0)
> -
> -#define SOFTWARE_FLAGS_SPR33			XE_REG(0x4f084)
> +#define TIMESTAMP_OVERRIDE					XE_REG(0x44074)
> +#define   TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	REG_GENMASK(15, 12)
> +#define   TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK		REG_GENMASK(9, 0)
>  
>  #define PCU_IRQ_OFFSET				0x444e0
>  #define GU_MISC_IRQ_OFFSET			0x444f0
>  #define   GU_MISC_GSE				REG_BIT(27)
>  
> -#define GFX_MSTR_IRQ				XE_REG(0x190010)
> -#define   MASTER_IRQ				REG_BIT(31)
> -#define   GU_MISC_IRQ				REG_BIT(29)
> -#define   DISPLAY_IRQ				REG_BIT(16)
> -#define   GT_DW_IRQ(x)				REG_BIT(x)
> -
> -#define DG1_MSTR_TILE_INTR			XE_REG(0x190008)
> -#define   DG1_MSTR_IRQ				REG_BIT(31)
> -#define   DG1_MSTR_TILE(t)			REG_BIT(t)
> +#define SOFTWARE_FLAGS_SPR33			XE_REG(0x4f084)
>  
> -#define TIMESTAMP_OVERRIDE					XE_REG(0x44074)
> -#define   TIMESTAMP_OVERRIDE_US_COUNTER_DENOMINATOR_MASK	REG_GENMASK(15, 12)
> -#define   TIMESTAMP_OVERRIDE_US_COUNTER_DIVIDER_MASK		REG_GENMASK(9, 0)
> +#define GU_CNTL					XE_REG(0x101010)
> +#define   LMEM_INIT				REG_BIT(7)
>  
>  #define GGC					XE_REG(0x108040)
>  #define   GMS_MASK				REG_GENMASK(15, 8)
>  #define   GGMS_MASK				REG_GENMASK(7, 6)
>  
> -#define GSMBASE					XE_REG(0x108100)
>  #define DSMBASE					XE_REG(0x1080C0)
>  #define   BDSM_MASK				REG_GENMASK64(63, 20)
>  
> +#define GSMBASE					XE_REG(0x108100)
> +
>  #define STOLEN_RESERVED				XE_REG(0x1082c0)
>  #define   WOPCM_SIZE_MASK			REG_GENMASK64(8, 7)
>  
> +#define MTL_RP_STATE_CAP			XE_REG(0x138000)
> +
> +#define MTL_GT_RPE_FREQUENCY			XE_REG(0x13800c)
> +
> +#define MTL_MEDIAP_STATE_CAP			XE_REG(0x138020)
> +#define   MTL_RPN_CAP_MASK			REG_GENMASK(24, 16)
> +#define   MTL_RP0_CAP_MASK			REG_GENMASK(8, 0)
> +
> +#define MTL_MPE_FREQUENCY			XE_REG(0x13802c)
> +#define   MTL_RPE_MASK				REG_GENMASK(8, 0)
> +
> +#define DG1_MSTR_TILE_INTR			XE_REG(0x190008)
> +#define   DG1_MSTR_IRQ				REG_BIT(31)
> +#define   DG1_MSTR_TILE(t)			REG_BIT(t)
> +
> +#define GFX_MSTR_IRQ				XE_REG(0x190010)
> +#define   MASTER_IRQ				REG_BIT(31)
> +#define   GU_MISC_IRQ				REG_BIT(29)
> +#define   DISPLAY_IRQ				REG_BIT(16)
> +#define   GT_DW_IRQ(x)				REG_BIT(x)
> +
> +#define PVC_RP_STATE_CAP			XE_REG(0x281014)
> +
>  #endif
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation