[Intel-xe] [RFC PATCH 2/4] drm/xe: Move setup_private_ppat functions to platform files
Francois Dugast
francois.dugast at intel.com
Fri Mar 3 14:50:13 UTC 2023
New files are created for platform specific functions, starting
with setup_private_ppat. This is an intermediate step before
introducing function pointers.
Signed-off-by: Francois Dugast <francois.dugast at intel.com>
---
drivers/gpu/drm/xe/Makefile | 3 ++
drivers/gpu/drm/xe/xe_gt.c | 43 +---------------------------
drivers/gpu/drm/xe/xe_platform.h | 13 +++++++++
drivers/gpu/drm/xe/xe_platform_mtl.c | 21 ++++++++++++++
drivers/gpu/drm/xe/xe_platform_pvc.c | 24 ++++++++++++++++
drivers/gpu/drm/xe/xe_platform_tgl.c | 21 ++++++++++++++
6 files changed, 83 insertions(+), 42 deletions(-)
create mode 100644 drivers/gpu/drm/xe/xe_platform.h
create mode 100644 drivers/gpu/drm/xe/xe_platform_mtl.c
create mode 100644 drivers/gpu/drm/xe/xe_platform_pvc.c
create mode 100644 drivers/gpu/drm/xe/xe_platform_tgl.c
diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile
index 18257cd7227d..c28831a10ae0 100644
--- a/drivers/gpu/drm/xe/Makefile
+++ b/drivers/gpu/drm/xe/Makefile
@@ -72,6 +72,9 @@ xe-y += xe_bb.o \
xe_module.o \
xe_pci.o \
xe_pcode.o \
+ xe_platform_mtl.o \
+ xe_platform_pvc.o \
+ xe_platform_tgl.o \
xe_pm.o \
xe_preempt_fence.o \
xe_pt.o \
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index ff2f464bf083..0eceb5789d15 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -31,6 +31,7 @@
#include "xe_migrate.h"
#include "xe_mmio.h"
#include "xe_mocs.h"
+#include "xe_platform.h"
#include "xe_reg_sr.h"
#include "xe_ring_ops.h"
#include "xe_sa.h"
@@ -93,48 +94,6 @@ int xe_gt_alloc(struct xe_device *xe, struct xe_gt *gt)
return 0;
}
-static void tgl_setup_private_ppat(struct xe_gt *gt)
-{
- /* TGL doesn't support LLC or AGE settings */
- xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_WB);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_UC);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg, GEN8_PPAT_WB);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg, GEN8_PPAT_WB);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg, GEN8_PPAT_WB);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg, GEN8_PPAT_WB);
-}
-
-static void pvc_setup_private_ppat(struct xe_gt *gt)
-{
- xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_UC);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_WB);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
- GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg,
- GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg,
- GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg,
- GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB);
-}
-
-static void mtl_setup_private_ppat(struct xe_gt *gt)
-{
- xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, MTL_PPAT_0_WB);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg,
- MTL_PPAT_1_WT | MTL_2_COH_1W);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg,
- MTL_PPAT_3_UC | MTL_2_COH_1W);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg,
- MTL_PPAT_0_WB | MTL_2_COH_1W);
- xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
- MTL_PPAT_0_WB | MTL_3_COH_2W);
-}
-
static void setup_private_ppat(struct xe_gt *gt)
{
struct xe_device *xe = gt_to_xe(gt);
diff --git a/drivers/gpu/drm/xe/xe_platform.h b/drivers/gpu/drm/xe/xe_platform.h
new file mode 100644
index 000000000000..d00377e807db
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_platform.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2023 Intel Corporation
+ */
+
+#ifndef _XE_PLATFORM_H_
+#define _XE_PLATFORM_H_
+
+void tgl_setup_private_ppat(struct xe_gt *gt);
+void pvc_setup_private_ppat(struct xe_gt *gt);
+void mtl_setup_private_ppat(struct xe_gt *gt);
+
+#endif /* _XE_PLATFORM_H_ */
diff --git a/drivers/gpu/drm/xe/xe_platform_mtl.c b/drivers/gpu/drm/xe/xe_platform_mtl.c
new file mode 100644
index 000000000000..acc244a6a257
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_platform_mtl.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "regs/xe_gt_regs.h"
+#include "xe_gt_ppat.h"
+#include "xe_mmio.h"
+
+void mtl_setup_private_ppat(struct xe_gt *gt)
+{
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, MTL_PPAT_0_WB);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg,
+ MTL_PPAT_1_WT | MTL_2_COH_1W);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg,
+ MTL_PPAT_3_UC | MTL_2_COH_1W);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg,
+ MTL_PPAT_0_WB | MTL_2_COH_1W);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
+ MTL_PPAT_0_WB | MTL_3_COH_2W);
+}
diff --git a/drivers/gpu/drm/xe/xe_platform_pvc.c b/drivers/gpu/drm/xe/xe_platform_pvc.c
new file mode 100644
index 000000000000..fcee1426f395
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_platform_pvc.c
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "regs/xe_gt_regs.h"
+#include "xe_gt_ppat.h"
+#include "xe_mmio.h"
+
+void pvc_setup_private_ppat(struct xe_gt *gt)
+{
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_UC);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_WB);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg,
+ GEN12_PPAT_CLOS(1) | GEN8_PPAT_WT);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg,
+ GEN12_PPAT_CLOS(1) | GEN8_PPAT_WB);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg,
+ GEN12_PPAT_CLOS(2) | GEN8_PPAT_WT);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg,
+ GEN12_PPAT_CLOS(2) | GEN8_PPAT_WB);
+}
diff --git a/drivers/gpu/drm/xe/xe_platform_tgl.c b/drivers/gpu/drm/xe/xe_platform_tgl.c
new file mode 100644
index 000000000000..7b909a1a90f4
--- /dev/null
+++ b/drivers/gpu/drm/xe/xe_platform_tgl.c
@@ -0,0 +1,21 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2021 Intel Corporation
+ */
+
+#include "regs/xe_gt_regs.h"
+#include "xe_gt_ppat.h"
+#include "xe_mmio.h"
+
+void tgl_setup_private_ppat(struct xe_gt *gt)
+{
+ /* TGL doesn't support LLC or AGE settings */
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(0).reg, GEN8_PPAT_WB);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(1).reg, GEN8_PPAT_WC);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(2).reg, GEN8_PPAT_WT);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(3).reg, GEN8_PPAT_UC);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(4).reg, GEN8_PPAT_WB);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(5).reg, GEN8_PPAT_WB);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(6).reg, GEN8_PPAT_WB);
+ xe_mmio_write32(gt, GEN12_PAT_INDEX(7).reg, GEN8_PPAT_WB);
+}
--
2.25.1
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