[Intel-xe] [PATCH] drm/xe: Fix size of xe_eu_mask_t

[Matt Roper]

On Fri, Mar 03, 2023 at 09:43:26AM -0800, Lucas De Marchi wrote:
> On Fri, Mar 03, 2023 at 09:05:55AM -0800, Jose Souza wrote:
> > XE_MAX_DSS_FUSE_REGS was being used to calculate the size of
> > xe_eu_mask_t while it should use XE_MAX_EU_FUSE_REGS.
> > There are no know issues about this but fixing it anyways.
> > 
> > Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> > ---
> > drivers/gpu/drm/xe/xe_gt_types.h | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> > index b01edd3fdc4d5..74b4e6776bf16 100644
> > --- a/drivers/gpu/drm/xe/xe_gt_types.h
> > +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> > @@ -31,7 +31,7 @@ enum xe_gt_type {
> > #define XE_MAX_EU_FUSE_REGS	1
> > 
> > typedef unsigned long xe_dss_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)];
> > -typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_DSS_FUSE_REGS)];
> > +typedef unsigned long xe_eu_mask_t[BITS_TO_LONGS(32 * XE_MAX_EU_FUSE_REGS)];
> 
> since XE_MAX_DSS_FUSE_REGS is 2 and XE_MAX_EU_FUSE_REGS is 1, I don't
> think it was triggering any bug... we were just using more space than we
> needed.
> 
> The fix looks good as the xe_eu_mask_t is supposed to be the eu mask
> *per DSS*. This comes from commit d44a3291d2a8 ("drm/xe/gt: Read topology from fuse registers")
> before the initial squash.
> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> 
> Lucas De Marchi
> 
> 
> > 
> > struct xe_mmio_range {
> > 	u32 start;
> > -- 
> > 2.39.2
> > 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation