[Intel-xe] [PATCH] drm/xe/mcr: Add L3BANK steering for DG2

[Matt Roper]

On Mon, Mar 06, 2023 at 05:56:35PM -0800, Lucas De Marchi wrote:
> Some register ranges with replication type L3BANK were missing from the
> driver table. The following warning was triggering when adding a
> workaround touching the register 0xb188:
> 
> 	xe 0000:03:00.0: Did not find MCR register 0xb188 in any MCR steering table
> 
> Add the L3BANK ranges according to the spec.
> 
> Bspec: 66534
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_gt_mcr.c | 7 +++++++
>  1 file changed, 7 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_gt_mcr.c b/drivers/gpu/drm/xe/xe_gt_mcr.c
> index fdbf9edb14cd..694a79b40ec0 100644
> --- a/drivers/gpu/drm/xe/xe_gt_mcr.c
> +++ b/drivers/gpu/drm/xe/xe_gt_mcr.c
> @@ -47,6 +47,12 @@ static const struct xe_mmio_range xelp_l3bank_steering_table[] = {
>  	{},
>  };
>  
> +static const struct xe_mmio_range xehp_l3bank_steering_table[] = {
> +	{ 0x008C80, 0x00BCFF },

I think there's a typo here.  Upper bound should be *8*CFF if I'm
reading the bspec correctly.

We also need a new clause in init_steering_l3bank() to select a
non-terminated instance properly (it differs from the other platforms
with L3BANK ranges).


Matt

> +	{ 0x00B100, 0x00B3FF },
> +	{},
> +};
> +
>  /*
>   * Although the bspec lists more "MSLICE" ranges than shown here, some of those
>   * are of a "GAM" subclass that has special rules and doesn't need to be
> @@ -277,6 +283,7 @@ void xe_gt_mcr_init(struct xe_gt *gt)
>  		gt->steering[INSTANCE0].ranges = xehpc_instance0_steering_table;
>  		gt->steering[DSS].ranges = xehpc_dss_steering_table;
>  	} else if (xe->info.platform == XE_DG2) {
> +		gt->steering[L3BANK].ranges = xehp_l3bank_steering_table;
>  		gt->steering[MSLICE].ranges = xehp_mslice_steering_table;
>  		gt->steering[LNCF].ranges = xehp_lncf_steering_table;
>  		gt->steering[DSS].ranges = xehp_dss_steering_table;
> -- 
> 2.39.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation