[Intel-xe] [PATCH 06/19] drm/xe/rtp: Add match for render reset domain

[Matt Roper]

On Tue, Mar 07, 2023 at 01:24:33AM -0800, Lucas De Marchi wrote:
> This allows to create WA/tuning rules that match the first engine that
> is either of compute or render class. This matters for platforms that
> don't have a render engine and that may have arbitrary compute engines
> fused off: some register programming need to be added to one of those
> engines.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hw_engine_types.h |  5 +++++
>  drivers/gpu/drm/xe/xe_rtp.c             | 10 ++++++++++
>  drivers/gpu/drm/xe/xe_rtp.h             | 18 ++++++++++++++++++
>  3 files changed, 33 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> index 05a2fdc381d7..2c40384957da 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> @@ -23,6 +23,7 @@ enum xe_engine_class {
>  
>  enum xe_hw_engine_id {
>  	XE_HW_ENGINE_RCS0,
> +#define XE_HW_ENGINE_RCS_MASK	GENMASK_ULL(XE_HW_ENGINE_RCS0, XE_HW_ENGINE_RCS0)
>  	XE_HW_ENGINE_BCS0,
>  	XE_HW_ENGINE_BCS1,
>  	XE_HW_ENGINE_BCS2,
> @@ -32,6 +33,7 @@ enum xe_hw_engine_id {
>  	XE_HW_ENGINE_BCS6,
>  	XE_HW_ENGINE_BCS7,
>  	XE_HW_ENGINE_BCS8,
> +#define XE_HW_ENGINE_BCS_MASK	GENMASK_ULL(XE_HW_ENGINE_BCS8, XE_HW_ENGINE_BCS0)
>  	XE_HW_ENGINE_VCS0,
>  	XE_HW_ENGINE_VCS1,
>  	XE_HW_ENGINE_VCS2,
> @@ -40,14 +42,17 @@ enum xe_hw_engine_id {
>  	XE_HW_ENGINE_VCS5,
>  	XE_HW_ENGINE_VCS6,
>  	XE_HW_ENGINE_VCS7,
> +#define XE_HW_ENGINE_VCS_MASK	GENMASK_ULL(XE_HW_ENGINE_VCS7, XE_HW_ENGINE_VCS0)
>  	XE_HW_ENGINE_VECS0,
>  	XE_HW_ENGINE_VECS1,
>  	XE_HW_ENGINE_VECS2,
>  	XE_HW_ENGINE_VECS3,
> +#define XE_HW_ENGINE_VECS_MASK	GENMASK_ULL(XE_HW_ENGINE_VECS3, XE_HW_ENGINE_VECS0)
>  	XE_HW_ENGINE_CCS0,
>  	XE_HW_ENGINE_CCS1,
>  	XE_HW_ENGINE_CCS2,
>  	XE_HW_ENGINE_CCS3,
> +#define XE_HW_ENGINE_CCS_MASK	GENMASK_ULL(XE_HW_ENGINE_CCS3, XE_HW_ENGINE_CCS0)
>  	XE_NUM_HW_ENGINES,
>  };
>  
> diff --git a/drivers/gpu/drm/xe/xe_rtp.c b/drivers/gpu/drm/xe/xe_rtp.c
> index c04eca290ef0..0d2f51bb06e8 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.c
> +++ b/drivers/gpu/drm/xe/xe_rtp.c
> @@ -160,3 +160,13 @@ bool xe_rtp_match_even_instance(const struct xe_gt *gt,
>  {
>  	return hwe->instance % 2 == 0;
>  }
> +
> +bool xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,
> +					  const struct xe_hw_engine *hwe)
> +{
> +	u64 render_compute_mask = gt->info.engine_mask &
> +		(XE_HW_ENGINE_CCS_MASK | XE_HW_ENGINE_RCS_MASK);
> +
> +	return render_compute_mask &&
> +		hwe->engine_id == __ffs(render_compute_mask);
> +}
> diff --git a/drivers/gpu/drm/xe/xe_rtp.h b/drivers/gpu/drm/xe/xe_rtp.h
> index 9bd2532442ed..433f0cbff57f 100644
> --- a/drivers/gpu/drm/xe/xe_rtp.h
> +++ b/drivers/gpu/drm/xe/xe_rtp.h
> @@ -409,4 +409,22 @@ void xe_rtp_process(const struct xe_rtp_entry *entries, struct xe_reg_sr *sr,
>  bool xe_rtp_match_even_instance(const struct xe_gt *gt,
>  				const struct xe_hw_engine *hwe);
>  
> +/*
> + * xe_rtp_match_first_render_or_compute - Match if it's first render or compute
> + * engine in the GT
> + *
> + * @gt: GT structure
> + * @hwe: Engine instance
> + *
> + * Registers on the render reset domain need to have their values re-applied
> + * when any of those engines are reset. Since the engines reset together, a
> + * programming can be set to just one of them. For simplicity the first engine
> + * of either render or compute class can be chosen.
> + *
> + * Returns: true if engine id is the first to match the render reset domain,
> + * false otherwise.
> + */
> +bool xe_rtp_match_first_render_or_compute(const struct xe_gt *gt,
> +					  const struct xe_hw_engine *hwe);
> +
>  #endif
> -- 
> 2.39.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation