[Intel-xe] [PATCH 14/19] drm/xe: Add PVC gt workarounds

[Lucas De Marchi]

On Wed, Mar 08, 2023 at 03:11:15PM -0800, Matt Roper wrote:
>On Tue, Mar 07, 2023 at 01:24:41AM -0800, Lucas De Marchi wrote:
>> Synchronize with i915 the PVC gt workarounds as of committ
>> commit 4d14d7717f19 ("drm/i915/selftest: Fix ktime_get() and h/w
>> access order").
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  9 +++++++++
>>  drivers/gpu/drm/xe/xe_wa.c           | 18 ++++++++++++++++++
>>  2 files changed, 27 insertions(+)
>>
>> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> index 70457c0ff4a6..1b39a209898b 100644
>> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
>> @@ -216,6 +216,15 @@
>>  #define FORCEWAKE_MEDIA_VDBOX_GEN11(n)		_MMIO(0xa540 + (n) * 4)
>>  #define FORCEWAKE_MEDIA_VEBOX_GEN11(n)		_MMIO(0xa560 + (n) * 4)
>>
>> +#define XEHPC_LNCFMISCCFGREG0			MCR_REG(0xb01c)
>> +#define   XEHPC_OVRLSCCC			REG_BIT(0)
>> +
>> +#define RENDER_MOD_CTRL				MCR_REG(0xcf2c)
>> +#define COMP_MOD_CTRL				MCR_REG(0xcf30)
>> +#define XEHP_VDBX_MOD_CTRL			MCR_REG(0xcf34)
>> +#define XEHP_VEBX_MOD_CTRL			MCR_REG(0xcf38)
>> +#define   FORCE_MISS_FTLB			REG_BIT(3)
>> +
>>  #define GEN10_SAMPLER_MODE			MCR_REG(0xe18c)
>>  #define   ENABLE_SMALLPL			REG_BIT(15)
>>  #define   SC_DISABLE_POWER_OPTIMIZATION_EBB	REG_BIT(9)
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index 155cabe16e2e..6498f187591d 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -180,6 +180,24 @@ static const struct xe_rtp_entry gt_was[] = {
>>  	  XE_RTP_RULES(PLATFORM(DG2)),
>>  	  XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
>>  	},
>> +
>> +	/* PVC */
>> +
>> +	{ XE_RTP_NAME("14015795083"),
>> +	  XE_RTP_RULES(PLATFORM(PVC)),
>> +	  XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
>> +	},
>> +	{ XE_RTP_NAME("18018781329"),
>> +	  XE_RTP_RULES(PLATFORM(PVC)),
>> +	  XE_RTP_ACTIONS(SET(RENDER_MOD_CTRL, FORCE_MISS_FTLB),
>> +			 SET(COMP_MOD_CTRL, FORCE_MISS_FTLB),
>> +			 SET(XEHP_VDBX_MOD_CTRL, FORCE_MISS_FTLB),
>> +			 SET(XEHP_VEBX_MOD_CTRL, FORCE_MISS_FTLB))
>> +	},
>> +	{ XE_RTP_NAME("16016694945"),
>> +	  XE_RTP_RULES(PLATFORM(PVC)),
>> +	  XE_RTP_ACTIONS(SET(XEHPC_LNCFMISCCFGREG0, XEHPC_OVRLSCCC))
>
>I think we need XE_RTP_ACTION_FLAG(MASKED_REG) on this one.

yeah, missed the flag in this one.

thanks
Lucas De Marchi

>
>
>Matt
>
>> +	},
>>  	{}
>>  };
>>
>> --
>> 2.39.0
>>
>
>-- 
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation