[Intel-xe] [PATCH v2 2/2] drm/xe: Add support for CCS engine fusing

[Lucas De Marchi]

On Wed, Mar 08, 2023 at 04:55:30PM -0800, Matt Roper wrote:
>For Xe_HP platforms that can have multiple CCS engines, the
>presence/absence of each CCS is inferred by the presence/absence of any
>DSS in the corresponding quadrant of the GT's DSS mask.
>
>This handling is only needed on platforms that can have more than one
>CCS.  The CCS is never fused off on platforms like MTL that can only
>have one.
>
>v2:
> - Add extra warnings to try to catch mistakes where the register counts
>   in get_num_dss_regs() are updated without corresponding updates to
>   the register parameters passed to load_dss_mask().  (Lucas)
> - Add kerneldoc for xe_gt_topology_has_dss_in_quadrant() and clarify
>   why we care about quadrants of the DSS space.  (Lucas)
> - Ensure CCS engine counting treats engine mask as 64-bit.  (Lucas)
>
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

thanks
Lucas De Marchi