[Intel-xe] [PATCH 13/19] drm/xe: Reorder WAs to consider the platform
Lucas De Marchi
lucas.demarchi at intel.com
Thu Mar 9 08:34:04 UTC 2023
On Wed, Mar 08, 2023 at 02:55:10PM -0800, Matt Roper wrote:
>On Tue, Mar 07, 2023 at 01:24:40AM -0800, Lucas De Marchi wrote:
>> Now that number of platforms is growing, it's getting hard to know the
>> workarounds for each platform. Split the entries inside the same table
>> so the workarounds checking IP version are listed first, followed by
>> each platform. Next step when it grows too much is to split in smaller
>> tables.
>>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>> ---
>> drivers/gpu/drm/xe/xe_wa.c | 93 ++++++++++++++++++++++----------------
>> 1 file changed, 54 insertions(+), 39 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>> index 67539f9d70b4..155cabe16e2e 100644
>> --- a/drivers/gpu/drm/xe/xe_wa.c
>> +++ b/drivers/gpu/drm/xe/xe_wa.c
>> @@ -99,6 +99,24 @@ static const struct xe_rtp_entry gt_was[] = {
>> XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F10(0), IECPUNIT_CLKGATE_DIS)),
>> XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
>> },
>> + { XE_RTP_NAME("14011059788"),
>> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
>> + XE_RTP_ACTIONS(SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
>> + },
>> +
>> + /* DG1 */
>> +
>> + { XE_RTP_NAME("1409420604"),
>> + XE_RTP_RULES(PLATFORM(DG1)),
>> + XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
>> + },
>> + { XE_RTP_NAME("1408615072"),
>> + XE_RTP_RULES(PLATFORM(DG1)),
>> + XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL))
>> + },
>> +
>> + /* DG2 */
>> +
>> { XE_RTP_NAME("16010515920"),
>> XE_RTP_RULES(SUBPLATFORM(DG2, G10),
>> STEP(A0, B0),
>> @@ -162,47 +180,15 @@ static const struct xe_rtp_entry gt_was[] = {
>> XE_RTP_RULES(PLATFORM(DG2)),
>> XE_RTP_ACTIONS(CLR(GEN7_MISCCPCTL, GEN12_DOP_CLOCK_GATE_RENDER_ENABLE))
>> },
>> - { XE_RTP_NAME("14011059788"),
>> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210)),
>> - XE_RTP_ACTIONS(SET(GEN10_DFR_RATIO_EN_AND_CHICKEN, DFR_DISABLE))
>> - },
>> - { XE_RTP_NAME("1409420604"),
>> - XE_RTP_RULES(PLATFORM(DG1)),
>> - XE_RTP_ACTIONS(SET(SUBSLICE_UNIT_LEVEL_CLKGATE2, CPSSUNIT_CLKGATE_DIS))
>> - },
>> - { XE_RTP_NAME("1408615072"),
>> - XE_RTP_RULES(PLATFORM(DG1)),
>> - XE_RTP_ACTIONS(SET(UNSLICE_UNIT_LEVEL_CLKGATE2, VSUNIT_CLKGATE_DIS_TGL))
>> - },
>> {}
>> };
>>
>> static const struct xe_rtp_entry engine_was[] = {
>> - { XE_RTP_NAME("14015227452"),
>> - XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
>> - XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
>> - XE_RTP_ACTION_FLAG(MASKED_REG)))
>> - },
>> - { XE_RTP_NAME("1606931601"),
>> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>> - XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
>> - XE_RTP_ACTION_FLAG(MASKED_REG)))
>> - },
>> { XE_RTP_NAME("22010931296, 18011464164, 14010919138"),
>> XE_RTP_RULES(GRAPHICS_VERSION(1200), ENGINE_CLASS(RENDER)),
>> XE_RTP_ACTIONS(SET(GEN7_FF_THREAD_MODE,
>> GEN12_FF_TESSELATION_DOP_GATE_DISABLE))
>> },
>> - { XE_RTP_NAME("14010826681, 1606700617, 22010271021"),
>> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>> - XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
>> - XE_RTP_ACTION_FLAG(MASKED_REG)))
>> - },
>> - { XE_RTP_NAME("18019627453"),
>> - XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
>> - XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
>> - XE_RTP_ACTION_FLAG(MASKED_REG)))
>> - },
>> { XE_RTP_NAME("1409804808"),
>> XE_RTP_RULES(GRAPHICS_VERSION(1200),
>> ENGINE_CLASS(RENDER),
>> @@ -217,6 +203,30 @@ static const struct xe_rtp_entry engine_was[] = {
>> XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, GEN12_DISABLE_TDL_PUSH,
>> XE_RTP_ACTION_FLAG(MASKED_REG)))
>> },
>> + { XE_RTP_NAME("1606931601"),
>> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(SET(GEN8_ROW_CHICKEN2, GEN12_DISABLE_EARLY_READ,
>> + XE_RTP_ACTION_FLAG(MASKED_REG)))
>> + },
>> + { XE_RTP_NAME("14010826681, 1606700617, 22010271021"),
>> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
>> + XE_RTP_ACTION_FLAG(MASKED_REG)))
>> + },
>> + { XE_RTP_NAME("1406941453"),
>> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL,
>> + XE_RTP_ACTION_FLAG(MASKED_REG)))
>> + },
>> + { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
>
>This one probably doesn't belong in this file at all. It's an
>i915-desired policy rather than a workaround. It should either go in
>the tuning file, or in a new policy file (if we decide we want "tuning"
>to stay focused on the bspec-documented suggestions).
>
>Wherever this moves, we should probably copy over the mega-comment from
>i915 since it was explicitly requested by the maintainers that we add
>that explanation.
noted, but that deserves another commit since this is simply reordering
the WAs. To avoid much churn I will add a commit before this one.
thanks
Lucas De Marchi
>
>
>Matt
>
>> + XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(SET(GEN7_FF_SLICE_CS_CHICKEN1,
>> + GEN9_FFSC_PERCTX_PREEMPT_CTRL,
>> + XE_RTP_ACTION_FLAG(MASKED_REG)))
>> + },
>> +
>> + /* TGL */
>> +
>> { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
>> XE_RTP_RULES(PLATFORM(TIGERLAKE), ENGINE_CLASS(RENDER)),
>> XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
>> @@ -224,6 +234,9 @@ static const struct xe_rtp_entry engine_was[] = {
>> GEN8_RC_SEMA_IDLE_MSG_DISABLE,
>> XE_RTP_ACTION_FLAG(MASKED_REG)))
>> },
>> +
>> + /* RKL */
>> +
>> { XE_RTP_NAME("1607297627, 1607030317, 1607186500"),
>> XE_RTP_RULES(PLATFORM(ROCKETLAKE), ENGINE_CLASS(RENDER)),
>> XE_RTP_ACTIONS(SET(RING_PSMI_CTL(RENDER_RING_BASE),
>> @@ -231,15 +244,17 @@ static const struct xe_rtp_entry engine_was[] = {
>> GEN8_RC_SEMA_IDLE_MSG_DISABLE,
>> XE_RTP_ACTION_FLAG(MASKED_REG)))
>> },
>> - { XE_RTP_NAME("1406941453"),
>> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1210), ENGINE_CLASS(RENDER)),
>> - XE_RTP_ACTIONS(SET(GEN10_SAMPLER_MODE, ENABLE_SMALLPL,
>> +
>> + /* DG2 */
>> +
>> + { XE_RTP_NAME("14015227452"),
>> + XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(SET(GEN9_ROW_CHICKEN4, XEHP_DIS_BBL_SYSPIPE,
>> XE_RTP_ACTION_FLAG(MASKED_REG)))
>> },
>> - { XE_RTP_NAME("FtrPerCtxtPreemptionGranularityControl"),
>> - XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, 1250), ENGINE_CLASS(RENDER)),
>> - XE_RTP_ACTIONS(SET(GEN7_FF_SLICE_CS_CHICKEN1,
>> - GEN9_FFSC_PERCTX_PREEMPT_CTRL,
>> + { XE_RTP_NAME("18019627453"),
>> + XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
>> + XE_RTP_ACTIONS(SET(GEN9_CS_DEBUG_MODE1, FF_DOP_CLOCK_GATE_DISABLE,
>> XE_RTP_ACTION_FLAG(MASKED_REG)))
>> },
>> {}
>> --
>> 2.39.0
>>
>
>--
>Matt Roper
>Graphics Software Engineer
>Linux GPU Platform Enablement
>Intel Corporation
More information about the Intel-xe
mailing list