[Intel-xe] [PATCH] drm/xe: Fix Alderlake-P and DG2 display info

[Jani Nikula]

On Thu, 16 Mar 2023, Maarten Lankhorst <maarten.lankhorst at linux.intel.com> wrote:
> DG2 has cdclk squash, without which we calculate the CDCLK wrongly.
> Alderlake-P is LPD, not gen 12 display.
>
> With those fixed, display should work on both and all problems that were
> uncovered by testing done from rebasing are fixed.
>
> Signed-off-by: Maarten Lankhorst <maarten.lankhorst at linux.intel.com>
> ---
>  drivers/gpu/drm/xe/xe_display.c | 10 +++++++++-
>  1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_display.c b/drivers/gpu/drm/xe/xe_display.c
> index f28553be858d..54ec8ba5d3f3 100644
> --- a/drivers/gpu/drm/xe/xe_display.c
> +++ b/drivers/gpu/drm/xe/xe_display.c
> @@ -482,19 +482,27 @@ void xe_display_info_init(struct xe_device *xe)
>  		xe->info.display = (struct xe_device_display_info) { GEN12_DISPLAY };
>  		break;
>  	case XE_ALDERLAKE_S:
> -	case XE_ALDERLAKE_P:
>  		xe->info.display = (struct xe_device_display_info) {
>  			GEN12_DISPLAY,
>  			.has_hti = 1,
>  			.has_psr_hw_tracking = 0,
>  		};
>  		break;
> +	case XE_ALDERLAKE_P:
> +		xe->info.display = (struct xe_device_display_info) {

All of these should probably have const in them to ensure the compound
literals are put in rodata.

BR,
Jani.

> +			XE_LPD,
> +			.has_cdclk_crawl = 1,
> +			.has_modular_fia = 1,
> +			.has_psr_hw_tracking = 0,
> +		};
> +		break;
>  	case XE_DG2:
>  		xe->info.display = (struct xe_device_display_info) {
>  			XE_LPD,
>  			.cpu_transcoder_mask =
>  				BIT(TRANSCODER_A) | BIT(TRANSCODER_B) |
>  				BIT(TRANSCODER_C) | BIT(TRANSCODER_D),
> +			.has_cdclk_squash = 1,
>  		};
>  		break;
>  	case XE_METEORLAKE:

-- 
Jani Nikula, Intel Open Source Graphics Center