[Intel-xe] [PATCH 6/6] drm/xe/mtl: Handle PAT_INDEX offset jump

[Das, Nirmoy]

On 3/24/2023 10:04 PM, Matt Roper wrote:
> Starting with MTL, the number of entries in the PAT table increased to
> 16.  The register offset jumped between index 7 and index 8, so a slight
> adjustment is needed to ensure the PAT_INDEX macros select the proper
> offset for the upper half of the table.
>
> Note that although there are 16 registers in the hardware, the driver is
> currently only asked to program the first 5, and we leave the rest at
> their hardware default values.  That means we don't actually touch the
> upper half of the PAT table in the driver today and this patch won't
> have any functional effect [yet].
>
> Bspec: 44235
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Nirmoy Das<nirmoy.das at intel.com>

> ---
>   drivers/gpu/drm/xe/xe_pat.c | 4 +++-
>   1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 645eb20aea8e..a713afdd0510 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -8,7 +8,9 @@
>   #include "xe_gt_mcr.h"
>   #include "xe_mmio.h"
>   
> -#define _PAT_INDEX(index)			(0x4800 + (index) * 4)
> +#define _PAT_INDEX(index)			_PICK_EVEN_2RANGES(index, 8, \
> +								   0x4800, 0x4804, \
> +								   0x4848, 0x484c)
>   
>   #define MTL_L4_POLICY_MASK			REG_GENMASK(3, 2)
>   #define MTL_PAT_3_UC				REG_FIELD_PREP(MTL_L4_POLICY_MASK, 3)