[Intel-xe] [PATCH 5/6] drm/xe/mtl: Fix PAT table coherency settings

[Das, Nirmoy]

On 3/24/2023 10:04 PM, Matt Roper wrote:
> Re-sync our MTL PAT table with the bspec.  1-way coherency should only
> be set on table entry 3.  We do not want an incorrect setting here to
> accidentally paper over other bugs elsewhere in the driver.
>
> Bspec: 45101
> Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
Reviewed-by: Nirmoy Das<nirmoy.das at intel.com>
> ---
>   drivers/gpu/drm/xe/xe_pat.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_pat.c b/drivers/gpu/drm/xe/xe_pat.c
> index 142cf11b5914..645eb20aea8e 100644
> --- a/drivers/gpu/drm/xe/xe_pat.c
> +++ b/drivers/gpu/drm/xe/xe_pat.c
> @@ -52,8 +52,8 @@ const u32 pvc_pat_table[] = {
>   
>   const u32 mtl_pat_table[] = {
>   	[0] = MTL_PAT_0_WB,
> -	[1] = MTL_PAT_1_WT | MTL_2_COH_1W,
> -	[2] = MTL_PAT_3_UC | MTL_2_COH_1W,
> +	[1] = MTL_PAT_1_WT,
> +	[2] = MTL_PAT_3_UC,
>   	[3] = MTL_PAT_0_WB | MTL_2_COH_1W,
>   	[4] = MTL_PAT_0_WB | MTL_3_COH_2W,
>   };