[Intel-xe] [PATCH 7/8] drm/xe/irq: Drop commented-out code for non-existent media engines

[Lucas De Marchi]

On Thu, Mar 30, 2023 at 11:24:04AM -0700, Matt Roper wrote:
>Although the hardware team has set aside some register bits for extra
>media engines, no platform supported by the Xe driver today has VCS4-7
>or VECS2-3.  Drop the corresponding code (which was already commented
>out); we can bring it back easily enough if such engines show up on a
>future platform.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/xe/xe_irq.c | 12 ------------
> 1 file changed, 12 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>index 9fac03b63e7e..02292e60e52c 100644
>--- a/drivers/gpu/drm/xe/xe_irq.c
>+++ b/drivers/gpu/drm/xe/xe_irq.c
>@@ -143,13 +143,7 @@ static void gt_irq_postinstall(struct xe_device *xe, struct xe_gt *gt)
> 		xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~dmask);
> 	xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg, ~dmask);
> 	xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg, ~dmask);
>-	//if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
>-	//	intel_uncore_write(uncore, VCS4_VCS5_INTR_MASK, ~dmask);
>-	//if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
>-	//	intel_uncore_write(uncore, VCS6_VCS7_INTR_MASK, ~dmask);
> 	xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg, ~dmask);
>-	//if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
>-	//	intel_uncore_write(uncore, VECS2_VECS3_INTR_MASK, ~dmask);
> 	if (ccs_mask & (BIT(0)|BIT(1)))
> 		xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~dmask);
> 	if (ccs_mask & (BIT(2)|BIT(3)))
>@@ -424,13 +418,7 @@ static void gt_irq_reset(struct xe_gt *gt)
> 		xe_mmio_write32(gt, XEHPC_BCS7_BCS8_INTR_MASK.reg, ~0);
> 	xe_mmio_write32(gt, VCS0_VCS1_INTR_MASK.reg,	~0);
> 	xe_mmio_write32(gt, VCS2_VCS3_INTR_MASK.reg,	~0);
>-//	if (HAS_ENGINE(gt, VCS4) || HAS_ENGINE(gt, VCS5))
>-//		xe_mmio_write32(xe, VCS4_VCS5_INTR_MASK.reg,   ~0);
>-//	if (HAS_ENGINE(gt, VCS6) || HAS_ENGINE(gt, VCS7))
>-//		xe_mmio_write32(xe, VCS6_VCS7_INTR_MASK.reg,   ~0);
> 	xe_mmio_write32(gt, VECS0_VECS1_INTR_MASK.reg,	~0);
>-//	if (HAS_ENGINE(gt, VECS2) || HAS_ENGINE(gt, VECS3))
>-//		xe_mmio_write32(xe, VECS2_VECS3_INTR_MASK.reg, ~0);
> 	if (ccs_mask & (BIT(0)|BIT(1)))
> 		xe_mmio_write32(gt, CCS0_CCS1_INTR_MASK.reg, ~0);
> 	if (ccs_mask & (BIT(2)|BIT(3)))
>-- 
>2.39.2
>