[Intel-xe] [PATCH 0/4] RFC: drm/xe/ras: Supporting RAS on XE.

[Lucas De Marchi]

On Tue, May 02, 2023 at 03:58:45PM -0400, Rodrigo Vivi wrote:
>On Tue, May 02, 2023 at 12:38:21PM +0300, Jani Nikula wrote:
>> On Wed, 26 Apr 2023, "Ghimiray, Himal Prasad" <himal.prasad.ghimiray at intel.com> wrote:
>> > Hi Jani,
>> >
>> > Is recommendation to create new .h file for error related registers ?
>> > Can I go ahead with adding file xe_gt_error_regs.h (GT, SOC, GSC) which explicitly mentions registers related to error handling ?
>>
>> I don't know what the best grouping for this stuff would be. Maybe I'd
>> go for grouping by hardware blocks rather than functionality like
>> errors. Cc: Lucas, Matt, Rodrigo, just to pick a few names who might
>> have a better idea.
>
>I believe the right way is to group by the IP block and/or reset domain,
>rather than by functionality.
>
>But Lucas is probably the best one to guide us here. He has some ideas
>of tools to generate the regs we use from specs and the organization
>might be impacted.

what currently guides me when adding registers is the "Graphics Register
Address Map" from bspec. Example: 53616

Note that what we currently have comes mostly from i915 after a lot of
re-organization and changes to adhere to the coding style and
conventions. But the per-file split was kept as is from i915, which I
believe was done by Matt Roper.

My long term goal is to have a tool to generate these headers directly
from the spec, but I think we are far from it as there are more urgent
things to be done.  So:

1) Don't dump everything in xe_regs.h. Just by looking at the offsets
    you can have a good idea where they should be located
2) Don't dump to the end of the header. Sort registers by offset
3) Don't add registers/bitfields that are not used in the code.
    Preferably add them together with the code that uses them
4) Follow the coding style in these files, now that they are mostly
    clean.

Lucas De Marchi