[Intel-xe] [PATCH v4 2/2] drm/xe: Set default MOCS value for copy cs instructions

[Souza, Jose]

On Thu, 2023-05-04 at 07:19 -0700, Matt Roper wrote:
> On Thu, May 04, 2023 at 07:12:27AM -0700, José Roberto de Souza wrote:
> > copy cs instructions that dont have a explict MOCS field will use this
> > default MOCS value.
> > 
> > This was mainly copied from i915 source code.
> 
> Nit:  It kind of seems like Xe has moved far enough away from the
> original i915 code that this sentence isn't really needed on either of
> these patches?

Removed on v5.

v5 was was needed because hwe->reg_lrc is initialized later and I only caught it on CI =/.
So there is some minor changes, can you take another look?

thank you

> 
> Reviewed-by: Matt Roper <matthew.d.roper at intel.com>
> 
> > 
> > v2:
> > - move to xe_hw_engine.c
> > - remove BLIT_CCTL auxiliary macros
> > - removed MASKED_REG
> > 
> > v3:
> > - rebased
> > 
> > v4:
> > - process workaround in hwe->reg_lrc
> > 
> > BSpec: 45807
> > Cc: Matt Roper <matthew.d.roper at intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> > ---
> >  drivers/gpu/drm/xe/regs/xe_engine_regs.h |  6 ++++++
> >  drivers/gpu/drm/xe/xe_hw_engine.c        | 20 ++++++++++++++++++++
> >  2 files changed, 26 insertions(+)
> > 
> > diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > index 717d560626cec..79873bf64e8dd 100644
> > --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > @@ -58,6 +58,12 @@
> >  
> >  #define RING_BBADDR(base)			XE_REG((base) + 0x140)
> >  #define RING_BBADDR_UDW(base)			XE_REG((base) + 0x168)
> > +
> > +/* Handling MOCS value in BLIT_CCTL like it was done CMD_CCTL */
> > +#define BLIT_CCTL(base)				XE_REG((base) + 0x204)
> > +#define   BLIT_CCTL_DST_MOCS_MASK		REG_GENMASK(14, 9)
> > +#define   BLIT_CCTL_SRC_MOCS_MASK		REG_GENMASK(6, 1)
> > +
> >  #define RING_EXECLIST_STATUS_LO(base)		XE_REG((base) + 0x234)
> >  #define RING_EXECLIST_STATUS_HI(base)		XE_REG((base) + 0x234 + 4)
> >  
> > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> > index d497f0289c372..a7d5d81335f47 100644
> > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> > @@ -277,6 +277,8 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
> >  	const u8 mocs_read_idx = gt->mocs.uc_index;
> >  	u32 ring_cmd_cctl_val = REG_FIELD_PREP(CMD_CCTL_WRITE_OVERRIDE_MASK, mocs_write_idx) |
> >  			        REG_FIELD_PREP(CMD_CCTL_READ_OVERRIDE_MASK, mocs_read_idx);
> > +	u32 blit_cctl_val = REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, mocs_write_idx) |
> > +			    REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, mocs_read_idx);
> >  	const struct xe_rtp_entry engine_was[] = {
> >  		/*
> >  		 * RING_CMD_CCTL specifies the default MOCS entry that will be
> > @@ -297,8 +299,26 @@ hw_engine_setup_default_state(struct xe_hw_engine *hwe)
> >  		},
> >  		{}
> >  	};
> > +	const struct xe_rtp_entry lrc_was[] = {
> > +		/*
> > +		 * Some blitter commands do not have a field for MOCS, those
> > +		 * commands will use MOCS index pointed by BLIT_CCTL.
> > +		 * BLIT_CCTL registers are needed to be programmed to un-cached.
> > +		 */
> > +		{ XE_RTP_NAME("BLIT_CCTL_default_MOCS"),
> > +		  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1200, XE_RTP_END_VERSION_UNDEFINED),
> > +			       ENGINE_CLASS(COPY)),
> > +		  XE_RTP_ACTIONS(FIELD_SET(BLIT_CCTL(0),
> > +				 BLIT_CCTL_DST_MOCS_MASK |
> > +				 BLIT_CCTL_SRC_MOCS_MASK,
> > +				 blit_cctl_val,
> > +				 XE_RTP_ACTION_FLAG(ENGINE_BASE)))
> > +		},
> > +		{}
> > +	};
> >  
> >  	xe_rtp_process(engine_was, &hwe->reg_sr, gt, hwe);
> > +	xe_rtp_process(lrc_was, &hwe->reg_lrc, gt, hwe);
> >  }
> >  
> >  static void hw_engine_init_early(struct xe_gt *gt, struct xe_hw_engine *hwe,
> > -- 
> > 2.40.1
> > 
>