[Intel-xe] [PATCH 5/7] fixup! drm/xe/display: Implement display support

[Rodrigo Vivi]

On Fri, Apr 28, 2023 at 11:23:30PM -0700, Lucas De Marchi wrote:
> With the move of display above xe_reg conversion in xe_mmio,
> it should use the new types everywhere.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

and this is the one that will likely conflict with the series from Jani
right?

I will try to merge his series today, then on your rebase you change
both this and the previous at once.

anyway, on the approach:

Acked-by: Rodrigo Vivi <rodrigo.vivi at intel.com>


> ---
>  drivers/gpu/drm/xe/display/xe_de.h | 89 +++++++++++++++++++-----------
>  1 file changed, 57 insertions(+), 32 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/display/xe_de.h b/drivers/gpu/drm/xe/display/xe_de.h
> index 0c76b0d24d96..e6021f6d031d 100644
> --- a/drivers/gpu/drm/xe/display/xe_de.h
> +++ b/drivers/gpu/drm/xe/display/xe_de.h
> @@ -14,79 +14,95 @@
>  #include "i915_reg.h"
>  
>  static inline u32
> -intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
>  {
> -	return xe_mmio_read32(to_gt(i915), reg.reg);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	return xe_mmio_read32(to_gt(i915), reg);
>  }
>  
>  static inline u64
>  intel_de_read64_2x32(struct drm_i915_private *i915,
> -		     i915_reg_t lower_reg, i915_reg_t upper_reg)
> +		     i915_reg_t i915_lower_reg, i915_reg_t i915_upper_reg)
>  {
> +	struct xe_reg lower_reg = XE_REG(i915_mmio_reg_offset(i915_lower_reg));
> +	struct xe_reg upper_reg = XE_REG(i915_mmio_reg_offset(i915_upper_reg));
>  	u32 upper, lower;
>  
> -	lower = xe_mmio_read32(to_gt(i915), lower_reg.reg);
> -	upper = xe_mmio_read32(to_gt(i915), upper_reg.reg);
> +	lower = xe_mmio_read32(to_gt(i915), lower_reg);
> +	upper = xe_mmio_read32(to_gt(i915), upper_reg);
>  	return (u64)upper << 32 | lower;
>  }
>  
>  static inline void
> -intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t i915_reg)
>  {
> -	xe_mmio_read32(to_gt(i915), reg.reg);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	xe_mmio_read32(to_gt(i915), reg);
>  }
>  
>  static inline void
> -intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> +intel_de_write(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
>  {
> -	xe_mmio_write32(to_gt(i915), reg.reg, val);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	xe_mmio_write32(to_gt(i915), reg, val);
>  }
>  
>  static inline u32
> -intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
> +intel_de_rmw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 clear, u32 set)
>  {
> -	return xe_mmio_rmw32(to_gt(i915), reg.reg, clear, set);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	return xe_mmio_rmw32(to_gt(i915), reg, clear, set);
>  }
>  
>  static inline int
> -intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
>  			   u32 mask, u32 value, unsigned int timeout)
>  {
> -	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
> -			      false);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> +			      timeout * USEC_PER_MSEC, NULL, false);
>  }
>  
>  static inline int
> -intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_register_fw(struct drm_i915_private *i915, i915_reg_t i915_reg,
>  			      u32 mask, u32 value, unsigned int timeout)
>  {
> -	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask, timeout * USEC_PER_MSEC, NULL,
> -			      false);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	return xe_mmio_wait32(to_gt(i915), reg, value, mask,
> +			      timeout * USEC_PER_MSEC, NULL, false);
>  }
>  
>  static inline int
> -__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
> +__intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t i915_reg,
>  			     u32 mask, u32 value,
>  			     unsigned int fast_timeout_us,
>  			     unsigned int slow_timeout_ms, u32 *out_value)
>  {
> -	return xe_mmio_wait32(to_gt(i915), reg.reg, value, mask,
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	return xe_mmio_wait32(to_gt(i915), reg, value, mask,
>  			      fast_timeout_us + 1000 * slow_timeout_ms,
>  			      out_value, false);
>  }
>  
>  static inline int
> -intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t i915_reg,
>  		      u32 mask, unsigned int timeout)
>  {
> -	return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
> +	return intel_de_wait_for_register(i915, i915_reg, mask, mask, timeout);
>  }
>  
>  static inline int
> -intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
> +intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t i915_reg,
>  			u32 mask, unsigned int timeout)
>  {
> -	return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
> +	return intel_de_wait_for_register(i915, i915_reg, mask, 0, timeout);
>  }
>  
>  /*
> @@ -98,19 +114,23 @@ intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
>   * a more localised lock guarding all access to that bank of registers.
>   */
>  static inline u32
> -intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t i915_reg)
>  {
> -	return xe_mmio_read32(to_gt(i915), reg.reg);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	return xe_mmio_read32(to_gt(i915), reg);
>  }
>  
>  static inline void
> -intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> +intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t i915_reg, u32 val)
>  {
> -	xe_mmio_write32(to_gt(i915), reg.reg, val);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	xe_mmio_write32(to_gt(i915), reg, val);
>  }
>  
>  static inline void
> -intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t i915_reg)
>  {
>  	/*
>  	 * Not implemented, requires lock on all reads/writes.
> @@ -120,15 +140,20 @@ intel_de_write_samevalue(struct drm_i915_private *i915, i915_reg_t reg)
>  }
>  
>  static inline u32
> -intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t reg)
> +intel_de_read_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg)
>  {
> -	return xe_mmio_read32(to_gt(i915), reg.reg);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	return xe_mmio_read32(to_gt(i915), reg);
>  }
>  
>  static inline void
> -intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
> +intel_de_write_notrace(struct drm_i915_private *i915, i915_reg_t i915_reg,
> +		       u32 val)
>  {
> -	xe_mmio_write32(to_gt(i915), reg.reg, val);
> +	struct xe_reg reg = XE_REG(i915_mmio_reg_offset(i915_reg));
> +
> +	xe_mmio_write32(to_gt(i915), reg, val);
>  }
>  
>  static inline int
> -- 
> 2.40.1
>