[Intel-xe] [PATCH 7/7] drm/xe: Fix indent in xe_hw_engine_print_state()

[Rodrigo Vivi]

On Fri, Apr 28, 2023 at 11:23:32PM -0700, Lucas De Marchi wrote:
> Fix the indent to align with open parenthesis, following the coding
> style.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>

if this lands first I change my devcoredump one...
Otherwise this will likely not get needed because I hope
that I'm fixing this there...

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_hw_engine.c | 66 +++++++++++++++----------------
>  1 file changed, 33 insertions(+), 33 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index e62662bc3a86..ca98160dc5ee 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -516,70 +516,70 @@ void xe_hw_engine_print_state(struct xe_hw_engine *hwe, struct drm_printer *p)
>  		return;
>  
>  	drm_printf(p, "%s (physical), logical instance=%d\n", hwe->name,
> -		hwe->logical_instance);
> +		   hwe->logical_instance);
>  	drm_printf(p, "\tForcewake: domain 0x%x, ref %d\n",
> -		hwe->domain,
> -		xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
> +		   hwe->domain,
> +		   xe_force_wake_ref(gt_to_fw(hwe->gt), hwe->domain));
>  	drm_printf(p, "\tMMIO base: 0x%08x\n", hwe->mmio_base);
>  
>  	drm_printf(p, "\tHWSTAM: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
> +		   hw_engine_mmio_read32(hwe, RING_HWSTAM(0)));
>  	drm_printf(p, "\tRING_HWS_PGA: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
> +		   hw_engine_mmio_read32(hwe, RING_HWS_PGA(0)));
>  
>  	drm_printf(p, "\tRING_EXECLIST_STATUS_LO: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
> +		   hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_LO(0)));
>  	drm_printf(p, "\tRING_EXECLIST_STATUS_HI: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
> +		   hw_engine_mmio_read32(hwe, RING_EXECLIST_STATUS_HI(0)));
>  	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_LO: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe,
> +		   hw_engine_mmio_read32(hwe,
>  					 RING_EXECLIST_SQ_CONTENTS_LO(0)));
>  	drm_printf(p, "\tRING_EXECLIST_SQ_CONTENTS_HI: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe,
> +		   hw_engine_mmio_read32(hwe,
>  					 RING_EXECLIST_SQ_CONTENTS_HI(0)));
>  	drm_printf(p, "\tRING_EXECLIST_CONTROL: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
> +		   hw_engine_mmio_read32(hwe, RING_EXECLIST_CONTROL(0)));
>  
>  	drm_printf(p, "\tRING_START: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_START(0)));
> +		   hw_engine_mmio_read32(hwe, RING_START(0)));
>  	drm_printf(p, "\tRING_HEAD:  0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
> +		   hw_engine_mmio_read32(hwe, RING_HEAD(0)) & HEAD_ADDR);
>  	drm_printf(p, "\tRING_TAIL:  0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
> +		   hw_engine_mmio_read32(hwe, RING_TAIL(0)) & TAIL_ADDR);
>  	drm_printf(p, "\tRING_CTL: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_CTL(0)));
> +		   hw_engine_mmio_read32(hwe, RING_CTL(0)));
>  	drm_printf(p, "\tRING_MODE: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
> +		   hw_engine_mmio_read32(hwe, RING_MI_MODE(0)));
>  	drm_printf(p, "\tRING_MODE_GEN7: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_MODE(0)));
> +		   hw_engine_mmio_read32(hwe, RING_MODE(0)));
>  
>  	drm_printf(p, "\tRING_IMR:   0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_IMR(0)));
> +		   hw_engine_mmio_read32(hwe, RING_IMR(0)));
>  	drm_printf(p, "\tRING_ESR:   0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_ESR(0)));
> +		   hw_engine_mmio_read32(hwe, RING_ESR(0)));
>  	drm_printf(p, "\tRING_EMR:   0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_EMR(0)));
> +		   hw_engine_mmio_read32(hwe, RING_EMR(0)));
>  	drm_printf(p, "\tRING_EIR:   0x%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_EIR(0)));
> -
> -        drm_printf(p, "\tACTHD:  0x%08x_%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
> -		hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
> -        drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
> -		hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
> -        drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> -		hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
> -		hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
> +		   hw_engine_mmio_read32(hwe, RING_EIR(0)));
> +
> +	drm_printf(p, "\tACTHD:  0x%08x_%08x\n",
> +		   hw_engine_mmio_read32(hwe, RING_ACTHD_UDW(0)),
> +		   hw_engine_mmio_read32(hwe, RING_ACTHD(0)));
> +	drm_printf(p, "\tBBADDR: 0x%08x_%08x\n",
> +		   hw_engine_mmio_read32(hwe, RING_BBADDR_UDW(0)),
> +		   hw_engine_mmio_read32(hwe, RING_BBADDR(0)));
> +	drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> +		   hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0)),
> +		   hw_engine_mmio_read32(hwe, RING_DMA_FADD(0)));
>  
>  	drm_printf(p, "\tIPEIR: 0x%08x\n",
> -		hw_engine_mmio_read32(hwe, IPEIR(0)));
> +		   hw_engine_mmio_read32(hwe, IPEIR(0)));
>  	drm_printf(p, "\tIPEHR: 0x%08x\n\n",
> -		hw_engine_mmio_read32(hwe, IPEHR(0)));
> +		   hw_engine_mmio_read32(hwe, IPEHR(0)));
>  
>  	if (hwe->class == XE_ENGINE_CLASS_COMPUTE)
>  		drm_printf(p, "\tRCU_MODE: 0x%08x\n",
> -			xe_mmio_read32(hwe->gt, RCU_MODE));
> +			   xe_mmio_read32(hwe->gt, RCU_MODE));
>  
>  }
>  
> -- 
> 2.40.1
>