[Intel-xe] [PATCH] drm/xe: Move Media GuC register definition to proper header

[Lucas De Marchi]

On Thu, May 11, 2023 at 09:20:15PM +0200, Michal Wajdeczko wrote:
>All register definitions shall be kept in dedicated regs.h files,

That is not the rule. Yet.  In the commit message, I'd just say this
guc register can bem moved together with the rest of the register
definitions and be named in a similar way.

git grep "define.*XE_REG(" -- \
	drivers/gpu/drm/xe \
	':(exclude)drivers/gpu/drm/xe/regs' \
	':(exclude)drivers/gpu/drm/xe/compat-i915-headers' \
	':(exclude)drivers/gpu/drm/xe/tests'

drivers/gpu/drm/xe/xe_ggtt.c:#define GUC_TLB_INV_CR                             XE_REG(0xcee8)
drivers/gpu/drm/xe/xe_ggtt.c:#define PVC_GUC_TLB_INV_DESC0                      XE_REG(0xcf7c)
drivers/gpu/drm/xe/xe_ggtt.c:#define PVC_GUC_TLB_INV_DESC1                      XE_REG(0xcf80)
drivers/gpu/drm/xe/xe_gt_mcr.c:#define STEER_SEMAPHORE          XE_REG(0xFD0)
drivers/gpu/drm/xe/xe_guc.c:#define MEDIA_GUC_HOST_INTERRUPT        XE_REG(0x190304)
drivers/gpu/drm/xe/xe_guc_pc.c:#define GEN6_RP_STATE_CAP        XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5998)
drivers/gpu/drm/xe/xe_guc_pc.c:#define GEN10_FREQ_INFO_REC      XE_REG(MCHBAR_MIRROR_BASE_SNB + 0x5ef0)
drivers/gpu/drm/xe/xe_guc_pc.c:#define GEN12_RPSTAT1            XE_REG(0x1381b4)
drivers/gpu/drm/xe/xe_guc_pc.c:#define MTL_MIRROR_TARGET_WP1    XE_REG(0xc60)
drivers/gpu/drm/xe/xe_irq.c:#define IMR(offset)                         XE_REG(offset + 0x4)
drivers/gpu/drm/xe/xe_irq.c:#define IIR(offset)                         XE_REG(offset + 0x8)
drivers/gpu/drm/xe/xe_irq.c:#define IER(offset)                         XE_REG(offset + 0xc)
drivers/gpu/drm/xe/xe_mmio.c:#define XEHP_MTCFG_ADDR            XE_REG(0x101800)
drivers/gpu/drm/xe/xe_pcode_api.h:#define PCODE_MAILBOX                 XE_REG(0x138124)
drivers/gpu/drm/xe/xe_pcode_api.h:#define PCODE_DATA0                   XE_REG(0x138128)
drivers/gpu/drm/xe/xe_pcode_api.h:#define PCODE_DATA1                   XE_REG(0x13812C)
drivers/gpu/drm/xe/xe_reg_whitelist.c:#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
drivers/gpu/drm/xe/xe_tuning.c:#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)
drivers/gpu/drm/xe/xe_wa.c:#define XE_REG_MCR(...)     XE_REG(__VA_ARGS__, .mcr = 1)

>not defined locally in .c files. While at it, rename it to match
>name from the Bspec.
>
>Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>
>---
> drivers/gpu/drm/xe/regs/xe_guc_regs.h | 2 ++
> drivers/gpu/drm/xe/xe_guc.c           | 4 +---
> 2 files changed, 3 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/regs/xe_guc_regs.h b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>index 37e0ac550931..01a8b0679679 100644
>--- a/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>+++ b/drivers/gpu/drm/xe/regs/xe_guc_regs.h
>@@ -122,6 +122,8 @@ struct guc_doorbell_info {
> #define MED_VF_SW_FLAG(n)			XE_REG(0x190310 + (n) * 4)
> #define MED_VF_SW_FLAG_COUNT			4
>
>+#define MED_GUC_HOST_INTERRUPT			XE_REG(0x190304)

wrong placement as registers should be sorted by the address,
so above this register.

Lucas De Marchi

>+
> /* GuC Interrupt Vector */
> #define GUC_INTR_GUC2HOST			BIT(15)
> #define GUC_INTR_EXEC_ERROR			BIT(14)
>diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
>index eb4af4c71124..18bce8c1fbf7 100644
>--- a/drivers/gpu/drm/xe/xe_guc.c
>+++ b/drivers/gpu/drm/xe/xe_guc.c
>@@ -22,8 +22,6 @@
> #include "xe_uc_fw.h"
> #include "xe_wopcm.h"
>
>-#define MEDIA_GUC_HOST_INTERRUPT        XE_REG(0x190304)
>-
> static struct xe_gt *
> guc_to_gt(struct xe_guc *guc)
> {
>@@ -268,7 +266,7 @@ int xe_guc_init(struct xe_guc *guc)
> 	guc_init_params(guc);
>
> 	if (xe_gt_is_media_type(gt))
>-		guc->notify_reg = MEDIA_GUC_HOST_INTERRUPT;
>+		guc->notify_reg = MED_GUC_HOST_INTERRUPT;
> 	else
> 		guc->notify_reg = GUC_HOST_INTERRUPT;
>
>-- 
>2.25.1
>