[Intel-xe] [PATCH 06/26] drm/xe: Move VRAM from GT to tile
Lucas De Marchi
lucas.demarchi at intel.com
Mon May 15 22:40:16 UTC 2023
On Wed, May 10, 2023 at 08:47:02PM -0700, Matt Roper wrote:
>On platforms with VRAM, the VRAM is associated with the tile, not the
>GT.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> drivers/gpu/drm/xe/Makefile | 1 +
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 6 +-
> drivers/gpu/drm/xe/display/xe_plane_initial.c | 8 +-
I'm not sure the best way to handle the display. On my refactors I've
been leaving them on a separate patch, even if it breaks the build. The
reason is that when the rebase happens and display is moved up, we don't
risk losing the these hunks.
>diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
>index 2481b2045284..6b9e7847161c 100644
>--- a/drivers/gpu/drm/xe/xe_device_types.h
>+++ b/drivers/gpu/drm/xe/xe_device_types.h
>@@ -53,6 +53,8 @@
> const struct xe_tile *: (const struct xe_device *)((tile__)->xe), \
> struct xe_tile *: (tile__)->xe)
>
>+struct xe_ggtt;
>+
> /**
> * struct xe_tile - hardware tile structure
> *
>@@ -96,6 +98,40 @@ struct xe_tile {
> /** @regs: pointer to tile's MMIO space (starting with registers) */
> void *regs;
> } mmio;
>+
>+ /** @mem: memory management info for tile */
>+ struct {
>+ /**
>+ * @vram: VRAM info for tile.
>+ *
>+ * Although VRAM is associated with a specific tile, it can
>+ * still be accessed by all tiles' GTs.
>+ */
>+ struct {
>+ /** @io_start: IO start address of this VRAM instance */
>+ resource_size_t io_start;
>+ /**
>+ * @io_size: IO size of this VRAM instance
>+ *
>+ * This represents how much of this VRAM we can access
>+ * via the CPU through the VRAM BAR. This can be smaller
>+ * than @size, in which case only part of VRAM is CPU
>+ * accessible (typically the first 256M). This
>+ * configuration is known as small-bar.
>+ */
>+ resource_size_t io_size;
>+ /** @size: size of VRAM. */
>+ resource_size_t size;
>+ /** @mapping: pointer to VRAM mappable space */
>+ void *__iomem mapping;
>+ } vram;
>+
>+ /** @vram_mgr: VRAM TTM manager */
>+ struct xe_ttm_vram_mgr *vram_mgr;
>+
>+ /** @ggtt: Global graphics translation table */
>+ struct xe_ggtt *ggtt;
I guess the ggtt should be moved on a separate patch?
other than that it seems good to me, but since it has a lot of
mechanical changes, but not CI, hard to judge for correctness.
Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
Lucas De Marchi
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