[Intel-xe] [PATCH 3/4] drm/xe: Size GT device memory correctly
Matthew Auld
matthew.auld at intel.com
Tue May 16 09:17:52 UTC 2023
On 15/05/2023 20:26, Michael J. Ruhl wrote:
> The current method of sizing GT device memory is not quite right.
>
> Update the algorithm to use the relevant HW information and offsets
> to set up the sizing correctly.
>
> Update the stolen memory sizing to reflect the changes, and to be
> GT specific.
>
> Signed-off-by: Michael J. Ruhl <michael.j.ruhl at intel.com>
Reviewed-by: Matthew Auld <matthew.auld at intel.com>
> ---
> drivers/gpu/drm/xe/xe_device_types.h | 2 +
> drivers/gpu/drm/xe/xe_gt_types.h | 2 +
> drivers/gpu/drm/xe/xe_mmio.c | 91 ++++++++++++++--------------
> 3 files changed, 49 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index a10ce67f11df..b00a23199492 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -203,6 +203,8 @@ struct xe_device {
> resource_size_t io_size;
> /** @size: Total size of VRAM */
> resource_size_t size;
> + /** @base: Offset to apply for Device Physical Address control */
> + resource_size_t base;
> /** @mapping: pointer to VRAM mappable space */
> void *__iomem mapping;
> } vram;
> diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h
> index 4b66e059ba9b..47f059bb8c6d 100644
> --- a/drivers/gpu/drm/xe/xe_gt_types.h
> +++ b/drivers/gpu/drm/xe/xe_gt_types.h
> @@ -155,6 +155,8 @@ struct xe_gt {
> * the first 256M). This configuration is known as small-bar.
> */
> resource_size_t io_size;
> + /** @base: offset of VRAM starting base */
> + resource_size_t base;
> /** @size: size of VRAM. */
> resource_size_t size;
> /** @mapping: pointer to VRAM mappable space */
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index c8b0eb5aab36..02fe2e71abe2 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -185,6 +185,8 @@ static int xe_determine_lmem_bar_size(struct xe_device *xe)
> if (!xe->mem.vram.io_size)
> return -EIO;
>
> + xe->mem.vram.base = 0; /* DPA offset */
> +
> /* set up a map to the total memory area. */
> xe->mem.vram.mapping = ioremap_wc(xe->mem.vram.io_start, xe->mem.vram.io_size);
>
> @@ -246,6 +248,9 @@ int xe_mmio_tile_vram_size(struct xe_gt *gt, u64 *vram_size, u64 *tile_size, u64
>
> int xe_mmio_probe_vram(struct xe_device *xe)
> {
> + resource_size_t io_size;
> + u64 available_size = 0;
> + u64 total_size = 0;
> struct xe_gt *gt;
> u64 tile_offset;
> u64 tile_size;
> @@ -271,64 +276,58 @@ int xe_mmio_probe_vram(struct xe_device *xe)
> drm_warn(&xe->drm, "Restricting VRAM size to PCI resource size (0x%llx->0x%llx)\n",
> vram_size, (u64)xe->mem.vram.io_size);
>
> - /* Limit size to available memory to account for the current memory algorithm */
> - xe->mem.vram.io_size = min_t(u64, xe->mem.vram.io_size, vram_size);
> - xe->mem.vram.size = xe->mem.vram.io_size;
> -
> drm_info(&xe->drm, "VISIBLE VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> &xe->mem.vram.io_size);
>
> - /* FIXME: Assuming equally partitioned VRAM, incorrect */
> - if (xe->info.tile_count > 1) {
> - u8 adj_tile_count = xe->info.tile_count;
> - resource_size_t size, io_start, io_size;
> + io_size = xe->mem.vram.io_size;
>
> - for_each_gt(gt, xe, id)
> - if (xe_gt_is_media_type(gt))
> - --adj_tile_count;
> + /* gt specific ranges */
> + for_each_gt(gt, xe, id) {
> + if (xe_gt_is_media_type(gt))
> + continue;
>
> - XE_BUG_ON(!adj_tile_count);
> + err = xe_mmio_tile_vram_size(gt, &vram_size, &tile_size, &tile_offset);
> + if (err)
> + return err;
>
> - size = xe->mem.vram.size / adj_tile_count;
> - io_start = xe->mem.vram.io_start;
> - io_size = xe->mem.vram.io_size;
> + gt->mem.vram.io_start = xe->mem.vram.io_start + tile_offset;
> + gt->mem.vram.io_size = min_t(u64, vram_size, io_size);
>
> - for_each_gt(gt, xe, id) {
> - if (id && !xe_gt_is_media_type(gt)) {
> - io_size -= min(io_size, size);
> - io_start += io_size;
> - }
> + if (!gt->mem.vram.io_size) {
> + drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
> + return -ENODEV;
> + }
>
> - gt->mem.vram.size = size;
> -
> - /*
> - * XXX: multi-tile small-bar might be wild. Hopefully
> - * full tile without any mappable vram is not something
> - * we care about.
> - */
> -
> - gt->mem.vram.io_size = min(size, io_size);
> - if (io_size) {
> - gt->mem.vram.io_start = io_start;
> - gt->mem.vram.mapping = xe->mem.vram.mapping +
> - (io_start - xe->mem.vram.io_start);
> - } else {
> - drm_err(&xe->drm, "Tile without any CPU visible VRAM. Aborting.\n");
> - return -ENODEV;
> - }
> + gt->mem.vram.base = tile_offset;
> + gt->mem.vram.size = vram_size;
> + gt->mem.vram.mapping = xe->mem.vram.mapping + tile_offset;
>
> - drm_info(&xe->drm, "VRAM[%u, %u]: %pa, %pa\n",
> - id, gt->info.vram_id, >->mem.vram.io_start,
> - >->mem.vram.size);
> + drm_info(&xe->drm, "VRAM[%u, %u]: %pa, %pa\n", id, gt->info.vram_id,
> + >->mem.vram.io_start, >->mem.vram.size);
> +
> + if (gt->mem.vram.io_size < gt->mem.vram.size)
> + drm_info(&xe->drm, "VRAM[%u, %u]: CPU access limited to %pa\n", id,
> + gt->info.vram_id, >->mem.vram.io_size);
> +
> + /* calculate total size using tile size to get the correct HW sizing */
> + total_size += tile_size;
> + available_size += vram_size;
> +
> + if (total_size > xe->mem.vram.io_size) {
> + drm_warn(&xe->drm, "VRAM: %pa is larger than resource %pa\n",
> + &total_size, &xe->mem.vram.io_size);
> }
> - } else {
> - gt->mem.vram.size = xe->mem.vram.size;
> - gt->mem.vram.io_start = xe->mem.vram.io_start;
> - gt->mem.vram.io_size = xe->mem.vram.io_size;
> - gt->mem.vram.mapping = xe->mem.vram.mapping;
>
> - drm_info(&xe->drm, "VRAM: %pa\n", >->mem.vram.size);
> + io_size -= min_t(u64, tile_size, io_size);
> }
> +
> + xe->mem.vram.size = total_size;
> +
> + drm_info(&xe->drm, "Total VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> + &xe->mem.vram.size);
> + drm_info(&xe->drm, "Available VRAM: %pa, %pa\n", &xe->mem.vram.io_start,
> + &available_size);
> +
> return 0;
> }
>
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