[Intel-xe] [PATCH 19/26] drm/xe/irq: Untangle postinstall functions

[Lucas De Marchi]

On Wed, May 10, 2023 at 08:47:15PM -0700, Matt Roper wrote:
>The callstack for postinstall is a bit muddled with top-level device
>interrupt enablement happening within platform-specific functions called
>from the per-tile xe_gt_irq_postinstall() function.  If we pull
>top-level irq enablement up to xe_irq_postinstall where we'd expect it
>to be, we can eliminate some confusing layers of indirection.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> drivers/gpu/drm/xe/xe_irq.c | 35 +++++++----------------------------
> 1 file changed, 7 insertions(+), 28 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_irq.c b/drivers/gpu/drm/xe/xe_irq.c
>index 2549fd9fb5cd..58745a5add87 100644
>--- a/drivers/gpu/drm/xe/xe_irq.c
>+++ b/drivers/gpu/drm/xe/xe_irq.c
>@@ -122,7 +122,7 @@ static inline void xelp_intr_enable(struct xe_device *xe, bool stall)
> 		xe_mmio_read32(mmio, GFX_MSTR_IRQ);
> }
>
>-static void gt_irq_postinstall(struct xe_tile *tile)
>+void xe_gt_irq_postinstall(struct xe_tile *tile)

should probably squash in HEAD~2 patch adding the call to
xe_irq_postinstall()?

this is also seems to be named wrong:  xe_gt_* receiving as first arg a
xe_tile inside a file named xe_irq.c. Suggestion to rename it to
xe_irq_postinstall_tile().


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>


Lucas De Marchi



> {
> 	struct xe_device *xe = tile_to_xe(tile);
> 	struct xe_gt *mmio = tile->primary_gt;
>@@ -181,15 +181,6 @@ static void gt_irq_postinstall(struct xe_tile *tile)
> 	xe_mmio_write32(mmio, GUC_SG_INTR_MASK,  ~0);
> }
>
>-static void xelp_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
>-{
>-	/* TODO: PCH */
>-
>-	gt_irq_postinstall(tile);
>-
>-	xelp_intr_enable(xe, true);
>-}
>-
> static u32
> gt_engine_identity(struct xe_device *xe,
> 		   struct xe_gt *mmio,
>@@ -366,14 +357,6 @@ static void dg1_intr_enable(struct xe_device *xe, bool stall)
> 		xe_mmio_read32(mmio, DG1_MSTR_TILE_INTR);
> }
>
>-static void dg1_irq_postinstall(struct xe_device *xe, struct xe_tile *tile)
>-{
>-	gt_irq_postinstall(tile);
>-
>-	if (tile->id == 0)
>-		dg1_intr_enable(xe, true);
>-}
>-
> /*
>  * Top-level interrupt handler for Xe_LP+ and beyond.  These platforms have
>  * a "master tile" interrupt register which must be consulted before the
>@@ -512,16 +495,6 @@ static void xe_irq_reset(struct xe_device *xe)
> 	xe_display_irq_reset(xe);
> }
>
>-void xe_gt_irq_postinstall(struct xe_tile *tile)
>-{
>-	struct xe_device *xe = tile_to_xe(tile);
>-
>-	if (GRAPHICS_VERx100(xe) >= 1210)
>-		dg1_irq_postinstall(xe, tile);
>-	else
>-		xelp_irq_postinstall(xe, tile);
>-}
>-
> static void xe_irq_postinstall(struct xe_device *xe)
> {
> 	struct xe_tile *tile;
>@@ -538,6 +511,12 @@ static void xe_irq_postinstall(struct xe_device *xe)
> 	 */
> 	unmask_and_enable(xe_device_get_root_tile(xe),
> 			  GU_MISC_IRQ_OFFSET, GU_MISC_GSE);
>+
>+	/* Enable top-level interrupts */
>+	if (GRAPHICS_VERx100(xe) >= 1210)
>+		dg1_intr_enable(xe, true);
>+	else
>+		xelp_intr_enable(xe, true);
> }
>
> static irq_handler_t xe_irq_handler(struct xe_device *xe)
>-- 
>2.40.0
>