[Intel-xe] [PATCH] drm/xe: Change GuC interrupt data

[Matt Roper]

On Fri, May 19, 2023 at 11:56:18AM +0200, Michal Wajdeczko wrote:
> Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass
> additional payload data to the GuC but this capability is not
> used by the firmware yet.
> 
> Stop using value mandated by legacy GuC interrupt register and
> use default notify value (zero) instead.
> 
> Bspec: 49813, 63363
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>

Looks like GUC_SEND_TRIGGER was only relevant to the old
HOST2GUC_INT_REG register (0xc4c8) that was used through gen9.  Should
we remove the #define for that bit from the header as well?

Aside from that,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_guc.c | 8 +++++++-
>  1 file changed, 7 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index eb4af4c71124..effd8b1ff59d 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -600,8 +600,14 @@ int xe_guc_suspend(struct xe_guc *guc)
>  void xe_guc_notify(struct xe_guc *guc)
>  {
>  	struct xe_gt *gt = guc_to_gt(guc);
> +	const u32 default_notify_data = 0;
>  
> -	xe_mmio_write32(gt, guc->notify_reg, GUC_SEND_TRIGGER);
> +	/*
> +	 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass
> +	 * additional payload data to the GuC but this capability is not
> +	 * used by the firmware yet. Use default value in the meantime.
> +	 */
> +	xe_mmio_write32(gt, guc->notify_reg, default_notify_data);
>  }
>  
>  int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr)
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation