[Intel-xe] [PATCH 6/6] drm/xe/rpl: Add missing RPLP and RPLS entry in xe_wa_test

Srivatsa, Anusha anusha.srivatsa at intel.com
Fri May 26 18:17:28 UTC 2023



> -----Original Message-----
> From: De Marchi, Lucas <lucas.demarchi at intel.com>
> Sent: Friday, May 26, 2023 10:36 AM
> To: Srivatsa, Anusha <anusha.srivatsa at intel.com>
> Cc: intel-xe at lists.freedesktop.org
> Subject: Re: [Intel-xe] [PATCH 6/6] drm/xe/rpl: Add missing RPLP and RPLS entry
> in xe_wa_test
> 
> On Fri, May 26, 2023 at 10:12:04AM -0700, Anusha Srivatsa wrote:
> >Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
> >---
> > drivers/gpu/drm/xe/tests/xe_wa_test.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c
> >b/drivers/gpu/drm/xe/tests/xe_wa_test.c
> >index 16f7f157c875..f86fa0f2ce10 100644
> >--- a/drivers/gpu/drm/xe/tests/xe_wa_test.c
> >+++ b/drivers/gpu/drm/xe/tests/xe_wa_test.c
> >@@ -58,6 +58,8 @@ static const struct platform_test_case cases[] = {
> > 	SUBPLATFORM_CASE(DG2, G11, B1),
> > 	SUBPLATFORM_CASE(DG2, G12, A0),
> > 	SUBPLATFORM_CASE(DG2, G12, A1),
> >+	SUBPLATFORM_CASE(ALDERLAKE_P, RPLU, E0),
> >+	SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
> 
> is the order correct here? RPL being a subplatform of ADL makes me think it
> should rather be grouped with the ADL ones above.
> 
> Also, ideally when we add a new platform we already go ahead and add it in the
> tests here. I'd either squash this commit with the addition of RPLS with a note
> that it's also adding the missing RPLU  or squash this into "drm/xe/adlp: Add
> missing ADL-P entry in xw_test_wa" with a different commit message: "drm/xe:
> Add ADL entries to xe_wa_test" and move it to be the last patch. We also can't
> have commits with empty commit message body. Something like this would
> suffice: "Now that all known Alderlake subplatforms are added, add them to the
> xe_wa_test kunit tests for checking their WAs".

Sure.

Anusha
> Lucas De Marchi
> 
> > 	PLATFORM_CASE(PVC, B0),
> > 	PLATFORM_CASE(PVC, B1),
> > 	PLATFORM_CASE(PVC, C0),
> >--
> >2.25.1
> >


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