[Intel-xe] [PATCH 10/12] drm/xe: Map the entire BAR0 and hold onto the initial mapping

[Matthew Brost]

On Wed, Nov 08, 2023 at 01:33:42AM +0100, Michał Winiarski wrote:
> Both MMIO registers and GGTT for root tile will need to be used earlier
> during probe. Don't rely on tile count to compute the mapping size.
> Further more, there's no need real need to remap after figuring out the
> real resource size.
> 
> Signed-off-by: Michał Winiarski <michal.winiarski at intel.com>

Good cleanup.

Reviewed-by: Matthew Brost <matthew.brost at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_mmio.c | 12 ++++--------
>  1 file changed, 4 insertions(+), 8 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mmio.c b/drivers/gpu/drm/xe/xe_mmio.c
> index ff968ef611cac..8945c601e1c54 100644
> --- a/drivers/gpu/drm/xe/xe_mmio.c
> +++ b/drivers/gpu/drm/xe/xe_mmio.c
> @@ -311,7 +311,6 @@ void xe_mmio_probe_tiles(struct xe_device *xe)
>  	size_t tile_mmio_size = SZ_16M, tile_mmio_ext_size = xe->info.tile_mmio_ext_size;
>  	u8 id, tile_count = xe->info.tile_count;
>  	struct xe_gt *gt = xe_root_mmio_gt(xe);
> -	const int mmio_bar = 0;
>  	struct xe_tile *tile;
>  	void *regs;
>  	u32 mtcfg;
> @@ -325,9 +324,6 @@ void xe_mmio_probe_tiles(struct xe_device *xe)
>  		if (tile_count < xe->info.tile_count) {
>  			drm_info(&xe->drm, "tile_count: %d, reduced_tile_count %d\n",
>  					xe->info.tile_count, tile_count);
> -			pci_iounmap(to_pci_dev(xe->drm.dev), xe->mmio.regs);
> -			xe->mmio.size = (tile_mmio_size + tile_mmio_ext_size) * tile_count;
> -			xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar, xe->mmio.size);
>  			xe->info.tile_count = tile_count;
>  
>  			/*
> @@ -374,17 +370,17 @@ static void mmio_fini(struct drm_device *drm, void *arg)
>  int xe_mmio_init(struct xe_device *xe)
>  {
>  	struct xe_tile *root_tile = xe_device_get_root_tile(xe);
> +	struct pci_dev *pdev = to_pci_dev(xe->drm.dev);
>  	const int mmio_bar = 0;
>  	int err;
>  
>  	/*
> -	 * Map the maximum expected BAR size, which will get remapped later
> -	 * if we determine that we're running on a reduced-tile system.
> +	 * Map the entire BAR.
>  	 * The first 16MB of the BAR, belong to the root tile, and include:
>  	 * registers (0-4MB), reserved space (4MB-8MB) and GGTT (8MB-16MB).
>  	 */
> -	xe->mmio.size = (SZ_16M + xe->info.tile_mmio_ext_size) * xe->info.tile_count;
> -	xe->mmio.regs = pci_iomap(to_pci_dev(xe->drm.dev), mmio_bar, xe->mmio.size);
> +	xe->mmio.size = pci_resource_len(pdev, mmio_bar);
> +	xe->mmio.regs = pci_iomap(pdev, mmio_bar, 0);
>  	if (xe->mmio.regs == NULL) {
>  		drm_err(&xe->drm, "failed to map registers\n");
>  		return -EIO;
> -- 
> 2.42.0
>