[Intel-xe] [PATCH v2 1/2] drm/xe/gsc: enable pvc support

[Daniele Ceraolo Spurio]

On 11/7/2023 11:02 PM, Usyskin, Alexander wrote:
>>> Configure and enable PVC HECI GSC support.
>>>
>>> Signed-off-by: Alexander Usyskin <alexander.usyskin at intel.com>
>>> ---
>>>    drivers/gpu/drm/xe/regs/xe_regs.h |  1 +
>>>    drivers/gpu/drm/xe/xe_heci_gsc.c  | 11 ++++++++++-
>>>    drivers/gpu/drm/xe/xe_pci.c       |  1 +
>>>    3 files changed, 12 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h
>> b/drivers/gpu/drm/xe/regs/xe_regs.h
>>> index a646d13af03a..ec9372aa739f 100644
>>> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
>>> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
>>> @@ -35,6 +35,7 @@
>>>    #define XEHPC_BCS8_RING_BASE			0x3ee000
>>>
>>>    #define DG1_GSC_HECI2_BASE                      0x00259000
>>> +#define PVC_GSC_HECI2_BASE                      0x00285000
>>>    #define DG2_GSC_HECI2_BASE                      0x00374000
>>>
>> Just noticed that these define are in the middle of the engine mmio base
>> defines. Might be cleaner to move them to a separate section, but not a
>> blocker
>>
> GSCCS_RING_BASE is not in the right place - I've been told that
> all defines should be sorted by value - it should be before BSD_RING_BASE 0x1c0000
>
>>>    #define GSCCS_RING_BASE				0x11a000
>>> diff --git a/drivers/gpu/drm/xe/xe_heci_gsc.c
>> b/drivers/gpu/drm/xe/xe_heci_gsc.c
>>> index 3328ddca42d0..d8e982e3d9a2 100644
>>> --- a/drivers/gpu/drm/xe/xe_heci_gsc.c
>>> +++ b/drivers/gpu/drm/xe/xe_heci_gsc.c
>>> @@ -70,6 +70,13 @@ static const struct heci_gsc_def heci_gsc_def_dg2 = {
>>>    	.bar_size = GSC_BAR_LENGTH,
>>>    };
>>>
>>> +static const struct heci_gsc_def heci_gsc_def_pvc = {
>>> +	.name = "mei-gscfi",
>>> +	.bar = PVC_GSC_HECI2_BASE,
>>> +	.bar_size = GSC_BAR_LENGTH,
>>> +	.slow_firmware = true,
>>> +};
>>> +
>>>    static void heci_gsc_release_dev(struct device *dev)
>>>    {
>>>    	struct auxiliary_device *aux_dev = to_auxiliary_dev(dev);
>>> @@ -172,7 +179,9 @@ void xe_heci_gsc_init(struct xe_device *xe)
>>>
>>>    	heci_gsc->irq = -1;
>>>
>>> -	if (xe->info.platform == XE_DG2) {
>>> +	if (xe->info.platform == XE_PVC) {
>>> +		def = &heci_gsc_def_pvc;
>> IIRC there are some power-related requirements for GSC in PVC. Is it
>> safe to use the GSC without implementing that? Or am I just
>> misunderstanding the requirements?
>>
> The RC6 workaround implementation is not planned on PVC Xe.
> RC6 will be disabled in this case.
> So, no need to implement mei workaround here.

sounds good.

Reviewed-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>

Daniele

>