[Intel-xe] [PATCH] drm/xe/xe2: Add workaround 14019449301

[Matt Roper]

On Fri, Nov 10, 2023 at 03:55:18PM +0530, Tejas Upadhyay wrote:
> This workaround applies to Xe2_LPM media-15, stepping-A0
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h | 3 +++
>  drivers/gpu/drm/xe/xe_wa.c           | 7 +++++++
>  2 files changed, 10 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 902c60543de0..cac6e9e3098c 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -446,6 +446,9 @@
>  #define XEHPC_BCS5_BCS6_INTR_MASK		XE_REG(0x190118)
>  #define XEHPC_BCS7_BCS8_INTR_MASK		XE_REG(0x19011c)
>  
> +#define XEHP_HRS_UNIT_LEVEL_CLKGATE		XE_REG(0x1c3f08)

This isn't the name of the register.  HRSunit clock gating is just one
single bit within the register.  You should name this with the same
convention as all the other vd clock gating registers.  Also, you've
provided only one specific offset here that applies to VD0.  You need to
make this parameterized engine register based on engine base.

> +#define HRSUNIT_CLKGATE_DIS			REG_BIT(5)
> +
>  #define PVC_GT0_PACKAGE_ENERGY_STATUS		XE_REG(0x281004)
>  #define PVC_GT0_PACKAGE_RAPL_LIMIT		XE_REG(0x281008)
>  #define PVC_GT0_PACKAGE_POWER_SKU_UNIT		XE_REG(0x281068)
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index d03e6674519f..5040d3841125 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -259,6 +259,13 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  	  XE_RTP_ACTIONS(SET(XELPMP_SQCNT1, ENFORCE_RAR))
>  	},
>  
> +	/* Xe2_LPM */
> +
> +	{ XE_RTP_NAME("14019449301"),
> +	  XE_RTP_RULES(MEDIA_VERSION(1500), MEDIA_STEP(A0, B0)),

There's no such thing as media version 15; Xe2_LPM is version 20.00.
And the bounds here don't match the workaround database either; this is
listed as being a permanent workaround, not one that goes away with B0
stepping.


Matt

> +	  XE_RTP_ACTIONS(SET(XEHP_HRS_UNIT_LEVEL_CLKGATE, HRSUNIT_CLKGATE_DIS))
> +	},
> +
>  	/* Xe2_LPG */
>  
>  	{ XE_RTP_NAME("16020975621"),
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation