[Intel-xe] [PATCH 4/4] drm/xe/guc: Use valid scratch register for posting read

[Matthew Brost]

On Wed, Nov 15, 2023 at 12:37:48PM +0100, Michal Wajdeczko wrote:
> There are only 4 scratch registers VF_SW_FLAG(0..3) on each GuC.
> We shouldn't use non-existing register VF_SW_FLAG(4) for posting
> read.
> 
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>

Reviewed-by: Matthew Brost <matthew.brost at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_guc.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 16c233f120c6..c05858847919 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -627,7 +627,7 @@ int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request,
>  	u32 header, reply;
>  	struct xe_reg reply_reg = xe_gt_is_media_type(gt) ?
>  		MED_VF_SW_FLAG(0) : VF_SW_FLAG(0);
> -	const u32 LAST_INDEX = VF_SW_FLAG_COUNT;
> +	const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1;
>  	int ret;
>  	int i;
>  
> -- 
> 2.25.1
>