[Intel-xe] [PATCH 2/3] drm/xe/mocs: Bring comment about mocs back to reality

[Matt Roper]

On Fri, Nov 17, 2023 at 09:40:48AM -0800, Lucas De Marchi wrote:
> The mocs documentation was copied from i915 and doesn't match the
> reality in xe. Reword it so it matches what the code is doing.
> 
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_mocs.c | 30 ++++++++++--------------------
>  1 file changed, 10 insertions(+), 20 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c
> index a072fbccc693..daf5f2a8c40a 100644
> --- a/drivers/gpu/drm/xe/xe_mocs.c
> +++ b/drivers/gpu/drm/xe/xe_mocs.c
> @@ -123,30 +123,20 @@ struct xe_mocs_info {
>   *
>   * These tables are intended to be kept reasonably consistent across
>   * HW platforms, and for ICL+, be identical across OSes. To achieve
> - * that, for Icelake and above, list of entries is published as part
> - * of bspec.
> + * that, list of entries is published as part of bspec.

s/list/the list/

>   *
> - * Entries not part of the following tables are undefined as far as
> - * userspace is concerned and shouldn't be relied upon.  For Gen < 12
> - * they will be initialized to PTE. Gen >= 12 don't have a setting for
> - * PTE and those platforms except TGL/RKL will be initialized L3 WB to
> - * catch accidental use of reserved and unused mocs indexes.
> - *
> - * The last few entries are reserved by the hardware. For ICL+ they
> - * should be initialized according to bspec and never used, for older
> - * platforms they should never be written to.
> + * Entries not part of the following tables are undefined as far as userspace is
> + * concerned and shouldn't be relied upon. The last few entries are reserved by
> + * the hardware. They should be initialized according to bspec and never used.
>   *
>   * NOTE1: These tables are part of bspec and defined as part of hardware

s/of hardware/of the hardware/


Aside from the two wording nitpicks,

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> - *       interface for ICL+. For older platforms, they are part of kernel
> - *       ABI. It is expected that, for specific hardware platform, existing
> - *       entries will remain constant and the table will only be updated by
> - *       adding new entries, filling unused positions.
> + * interface. It is expected that, for specific hardware platform, existing
> + * entries will remain constant and the table will only be updated by adding new
> + * entries, filling unused positions.
>   *
> - * NOTE2: For GEN >= 12 except TGL and RKL, reserved and unspecified MOCS
> - *       indices have been set to L3 WB. These reserved entries should never
> - *       be used, they may be changed to low performant variants with better
> - *       coherency in the future if more entries are needed.
> - *       For TGL/RKL, all the unspecified MOCS indexes are mapped to L3 UC.
> + * NOTE2: Reserved and unspecified MOCS indices have been set to L3 WB. These
> + * reserved entries should never be used. They may be changed to low performant
> + * variants with better coherency in the future if more entries are needed.
>   */
>  
>  static const struct xe_mocs_entry gen12_mocs_desc[] = {
> -- 
> 2.40.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation