[Intel-xe] [PATCH] drm/xe/dg2: Wa_18028616096 now applies to all DG2

[Gustavo Sousa]

Quoting Matt Roper (2023-11-15 15:30:30-03:00)
>The workaround database was just updated to extend this workaround to
>DG2-G11 (whereas previously it applied only to G10 and G12).
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>

Reviewed-by: Gustavo Sousa <gustavo.sousa at intel.com>

>---
> drivers/gpu/drm/xe/xe_wa.c | 7 +------
> 1 file changed, 1 insertion(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
>index d03e6674519f..6572715dfc09 100644
>--- a/drivers/gpu/drm/xe/xe_wa.c
>+++ b/drivers/gpu/drm/xe/xe_wa.c
>@@ -403,12 +403,7 @@ static const struct xe_rtp_entry_sr engine_was[] = {
>                              PERF_FIX_BALANCING_CFE_DISABLE))
>         },
>         { XE_RTP_NAME("18028616096"),
>-          XE_RTP_RULES(SUBPLATFORM(DG2, G10),
>-                       FUNC(xe_rtp_match_first_render_or_compute)),
>-          XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
>-        },
>-        { XE_RTP_NAME("18028616096"),
>-          XE_RTP_RULES(SUBPLATFORM(DG2, G12),
>+          XE_RTP_RULES(PLATFORM(DG2),
>                        FUNC(xe_rtp_match_first_render_or_compute)),
>           XE_RTP_ACTIONS(SET(LSC_CHICKEN_BIT_0_UDW, UGM_FRAGMENT_THRESHOLD_TO_3))
>         },
>-- 
>2.41.0
>