[Intel-xe] [CI 09/10] drm/xe/gsc: Define GSCCS for MTL

[Kandpal, Suraj]

> -----Original Message-----
> From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Daniele
> Ceraolo Spurio
> Sent: Saturday, November 18, 2023 4:22 AM
> To: intel-xe at lists.freedesktop.org
> Subject: [Intel-xe] [CI 09/10] drm/xe/gsc: Define GSCCS for MTL
> 
> Add the GSCCS to the media_xelpmp engine list. Note that since the GSCCS is
> only used with the GSC FW, we can consider it disabled if we don't have the
> FW available.
> 
> v2: mark GSCCS as allowed on the media IP in kunit tests
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio at intel.com>
> Cc: Alan Previn <alan.previn.teres.alexis at intel.com>
> Reviewed-by: John Harrison <John.C.Harrison at Intel.com>
> ---
>  drivers/gpu/drm/xe/tests/xe_pci_test.c |  9 +++------
>  drivers/gpu/drm/xe/xe_hw_engine.c      | 20 ++++++++++++++++++++
>  drivers/gpu/drm/xe/xe_pci.c            |  2 +-
>  3 files changed, 24 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/tests/xe_pci_test.c
> b/drivers/gpu/drm/xe/tests/xe_pci_test.c
> index 9c6f6c2c6c6e..98ecab51154e 100644
> --- a/drivers/gpu/drm/xe/tests/xe_pci_test.c
> +++ b/drivers/gpu/drm/xe/tests/xe_pci_test.c
> @@ -33,13 +33,10 @@ static void check_media_ip(const struct
> xe_media_desc *media)
>  	struct kunit *test = xe_cur_kunit();
>  	u64 mask = media->hw_engine_mask;
> 
> -	/*
> -	 * VCS and VECS engines are allowed on the media IP
> -	 *
> -	 * TODO:  Add GSCCS once support is added to the driver.
> -	 */
> +	/* VCS, VECS and GSCCS engines are allowed on the media IP */
>  	mask &= ~(XE_HW_ENGINE_VCS_MASK |
> -		  XE_HW_ENGINE_VECS_MASK);
> +		  XE_HW_ENGINE_VECS_MASK |
> +		  XE_HW_ENGINE_GSCCS_MASK);
> 
>  	/* Any remaining engines are an error */
>  	KUNIT_ASSERT_EQ(test, mask, 0);
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c
> b/drivers/gpu/drm/xe/xe_hw_engine.c
> index e831e63c5e48..c52c26c395a7 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -26,6 +26,7 @@
>  #include "xe_rtp.h"
>  #include "xe_sched_job.h"
>  #include "xe_tuning.h"
> +#include "xe_uc_fw.h"
>  #include "xe_wa.h"
> 
>  #define MAX_MMIO_BASES 3
> @@ -610,6 +611,24 @@ static void read_compute_fuses(struct xe_gt *gt)
>  		read_compute_fuses_from_dss(gt);
>  }
> 
> +static void check_gsc_availability(struct xe_gt *gt) {
> +	struct xe_device *xe = gt_to_xe(gt);
> +
> +	if (!(gt->info.engine_mask & BIT(XE_HW_ENGINE_GSCCS0)))
> +		return;
> +
> +	/*
> +	 * The GSCCS is only used to communicate with the GSC FW, so if we
> don't
> +	 * have the FW there is nothing we need the engine for and can
> therefore
> +	 * skip its initialization.
> +	 */
> +	if (!xe_uc_fw_is_available(&gt->uc.gsc.fw)) {
> +		gt->info.engine_mask &= ~BIT(XE_HW_ENGINE_GSCCS0);
> +		drm_info(&xe->drm, "gsccs disabled due to lack of FW\n");
> +	}
> +}
> +
>  int xe_hw_engines_init_early(struct xe_gt *gt)  {
>  	int i;
> @@ -617,6 +636,7 @@ int xe_hw_engines_init_early(struct xe_gt *gt)
>  	read_media_fuses(gt);
>  	read_copy_fuses(gt);
>  	read_compute_fuses(gt);
> +	check_gsc_availability(gt);
> 
>  	BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT <
> XE_HW_ENGINE_PREEMPT_TIMEOUT_MIN);
>  	BUILD_BUG_ON(XE_HW_ENGINE_PREEMPT_TIMEOUT >
> XE_HW_ENGINE_PREEMPT_TIMEOUT_MAX);
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c index
> 682ba188e456..406b4cd4c88a 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -197,7 +197,7 @@ static const struct xe_media_desc media_xelpmp = {
>  	.name = "Xe_LPM+",
>  	.hw_engine_mask =
>  		BIT(XE_HW_ENGINE_VCS0) | BIT(XE_HW_ENGINE_VCS2) |
> -		BIT(XE_HW_ENGINE_VECS0),	/* TODO: add GSC0 */
> +		BIT(XE_HW_ENGINE_VECS0) | BIT(XE_HW_ENGINE_GSCCS0)
>  };
> 

Do we have a function which checks if GSC CS is running or not for clients like HDCP to use

Regards,
Suraj Kandpal
>  static const struct xe_media_desc media_xe2 = {
> --
> 2.41.0