[Intel-xe] [PATCH V3] drm/xe/xe2: Add workaround 14019449301

Matt Roper matthew.d.roper at intel.com
Wed Nov 22 18:27:36 UTC 2023


On Tue, Nov 21, 2023 at 05:03:20PM +0530, Tejas Upadhyay wrote:
> This workaround applies to Xe2_LPM
> 
> V3(MattR):
>   - Reorder reg and wa placement
>   - Add base parameter to reg macro for better definition
> V2(MattR):
>   - Change name of register
>   - Loop for all engines
>   - Driver permanent WA, applies to all steps
> 
> Signed-off-by: Tejas Upadhyay <tejas.upadhyay at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 3 +++
>  drivers/gpu/drm/xe/xe_wa.c               | 8 ++++++++
>  2 files changed, 11 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index b57dec17eb2d..0035cfb89cf2 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -112,6 +112,9 @@
>  #define RING_EXECLIST_CONTROL(base)		XE_REG((base) + 0x550)
>  #define	  EL_CTRL_LOAD				REG_BIT(0)
>  
> +#define VDBOX_CGCTL3F08(base)			XE_REG((base) + 0x3f08)
> +#define   CG3DDISHRS_CLKGATE_DIS		REG_BIT(5)
> +
>  #define VDBOX_CGCTL3F10(base)			XE_REG((base) + 0x3f10)
>  #define   IECPUNIT_CLKGATE_DIS			REG_BIT(22)
>  
> diff --git a/drivers/gpu/drm/xe/xe_wa.c b/drivers/gpu/drm/xe/xe_wa.c
> index d03e6674519f..aea03a56c797 100644
> --- a/drivers/gpu/drm/xe/xe_wa.c
> +++ b/drivers/gpu/drm/xe/xe_wa.c
> @@ -273,6 +273,14 @@ static const struct xe_rtp_entry_sr gt_was[] = {
>  			 SET(XEHPC_L3CLOS_MASK(3), ~0))
>  	},
>  
> +	/* Xe2_LPM */
> +
> +	{ XE_RTP_NAME("14019449301"),
> +	  XE_RTP_RULES(MEDIA_VERSION(2000), ENGINE_CLASS(VIDEO_DECODE)),
> +	  XE_RTP_ACTIONS(SET(VDBOX_CGCTL3F08(0), CG3DDISHRS_CLKGATE_DIS)),
> +	  XE_RTP_ENTRY_FLAG(FOREACH_ENGINE),
> +	},
> +
>  	{}
>  };
>  
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation


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