[Intel-xe] [PATCH 1/3] drm/xe: Add device flag to indicate SR-IOV support

Matt Roper matthew.d.roper at intel.com
Wed Nov 22 19:38:00 UTC 2023


On Wed, Nov 15, 2023 at 08:38:02AM +0100, Michal Wajdeczko wrote:
> The Single Root I/O Virtualization (SR-IOV) extension to
> the PCI Express (PCIe) specification suite is supported
> starting from 12th generation of Intel Graphics processors.
> 
> Add a device flag that we will use to enable SR-IOV specific
> code paths and to indicate our readiness to support SR-IOV.
> 
> We will enable this flag for the specific platforms once all
> required changes and additions will be ready and merged.
> 
> Bspec: 52391
> Signed-off-by: Michal Wajdeczko <michal.wajdeczko at intel.com>

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

> ---
>  drivers/gpu/drm/xe/xe_device.h       | 5 +++++
>  drivers/gpu/drm/xe/xe_device_types.h | 2 ++
>  drivers/gpu/drm/xe/xe_pci.c          | 3 ++-
>  3 files changed, 9 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h
> index c4232de40ae0..54694f98c91a 100644
> --- a/drivers/gpu/drm/xe/xe_device.h
> +++ b/drivers/gpu/drm/xe/xe_device.h
> @@ -158,6 +158,11 @@ static inline bool xe_device_has_flat_ccs(struct xe_device *xe)
>  	return xe->info.has_flat_ccs;
>  }
>  
> +static inline bool xe_device_has_sriov(struct xe_device *xe)
> +{
> +	return xe->info.has_sriov;
> +}
> +
>  u32 xe_device_ccs_bytes(struct xe_device *xe, u64 size);
>  
>  #endif
> diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h
> index be11cadccbd4..f2ba4f746fa2 100644
> --- a/drivers/gpu/drm/xe/xe_device_types.h
> +++ b/drivers/gpu/drm/xe/xe_device_types.h
> @@ -253,6 +253,8 @@ struct xe_device {
>  		u8 has_llc:1;
>  		/** @has_range_tlb_invalidation: Has range based TLB invalidations */
>  		u8 has_range_tlb_invalidation:1;
> +		/** @has_sriov: Supports SR-IOV */
> +		u8 has_sriov:1;
>  		/** @enable_display: display enabled */
>  		u8 enable_display:1;
>  		/** @bypass_mtcfg: Bypass Multi-Tile configuration from MTCFG register */
> diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
> index 682ba188e456..c1c8048bbc0f 100644
> --- a/drivers/gpu/drm/xe/xe_pci.c
> +++ b/drivers/gpu/drm/xe/xe_pci.c
> @@ -60,6 +60,7 @@ struct xe_device_desc {
>  	u8 has_heci_gscfi:1;
>  
>  	u8 has_llc:1;
> +	u8 has_sriov:1;
>  	u8 bypass_mtcfg:1;
>  	u8 supports_mmio_ext:1;
>  };
> @@ -532,7 +533,6 @@ static void handle_gmdid(struct xe_device *xe,
>  	}
>  }
>  
> -
>  static int xe_info_init(struct xe_device *xe,
>  			const struct xe_device_desc *desc,
>  			const struct xe_subplatform_desc *subplatform_desc)
> @@ -578,6 +578,7 @@ static int xe_info_init(struct xe_device *xe,
>  	xe->info.graphics_name = graphics_desc->name;
>  	xe->info.media_name = media_desc ? media_desc->name : "none";
>  	xe->info.has_llc = desc->has_llc;
> +	xe->info.has_sriov = desc->has_sriov;
>  	xe->info.bypass_mtcfg = desc->bypass_mtcfg;
>  	xe->info.supports_mmio_ext = desc->supports_mmio_ext;
>  	xe->info.tile_mmio_ext_size = graphics_desc->tile_mmio_ext_size;
> -- 
> 2.25.1
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation


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