[Intel-xe] [PATCH 5/8] RFC drm/xe/uapi: Add configs for Engine busyness

[Riana Tauro]

GuC provides engine busyness ticks as a 64 bit counter which count
as clock ticks.

Add configs to the uapi to expose Engine busyness via PMU.

Cc: Aravind Iddamsetty <aravind.iddamsetty at linux.intel.com>
Signed-off-by: Riana Tauro <riana.tauro at intel.com>
---
 include/uapi/drm/xe_drm.h | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h
index 6f38f836b705..be75e6ed317f 100644
--- a/include/uapi/drm/xe_drm.h
+++ b/include/uapi/drm/xe_drm.h
@@ -1004,6 +1004,10 @@ struct drm_xe_wait_user_fence {
  *	fd = syscall(__NR_perf_event_open, &attr, -1, cpu, -1, 0);
  */
 
+enum drm_xe_pmu_engine_sample {
+	DRM_XE_PMU_SAMPLE_BUSY_TICKS = 0,
+};
+
 /*
  * Top bits of every counter are GT id.
  */
@@ -1012,6 +1016,22 @@ struct drm_xe_wait_user_fence {
 #define ___DRM_XE_PMU_OTHER(gt, x) \
 	(((__u64)(x)) | ((__u64)(gt) << __DRM_XE_PMU_GT_SHIFT))
 
+#define DRM_XE_PMU_SAMPLE_BITS (4)
+#define DRM_XE_PMU_SAMPLE_INSTANCE_BITS (8)
+#define DRM_XE_PMU_CLASS_SHIFT \
+	(DRM_XE_PMU_SAMPLE_BITS + DRM_XE_PMU_SAMPLE_INSTANCE_BITS)
+
+/*
+ * Engine configs offset - 0x1000
+ */
+#define DRM_XE_PMU_ENGINE_OFFSET(gt) \
+	(___DRM_XE_PMU_OTHER(gt, 0xfff) + 1)
+
+#define __DRM_XE_PMU_ENGINE(gt, class, instance, sample) \
+	(((class) << DRM_XE_PMU_CLASS_SHIFT | \
+	(instance) << DRM_XE_PMU_SAMPLE_BITS | \
+	(sample)) + DRM_XE_PMU_ENGINE_OFFSET(gt))
+
 #define DRM_XE_PMU_RENDER_GROUP_BUSY(gt)	___DRM_XE_PMU_OTHER(gt, 0)
 #define DRM_XE_PMU_COPY_GROUP_BUSY(gt)		___DRM_XE_PMU_OTHER(gt, 1)
 #define DRM_XE_PMU_MEDIA_GROUP_BUSY(gt)		___DRM_XE_PMU_OTHER(gt, 2)
-- 
2.40.0