[Intel-xe] [PATCH v2 2/3] drm/xe: Allow userspace to configure CCS mode
Niranjana Vishwanathapura
niranjana.vishwanathapura at intel.com
Wed Nov 29 02:57:15 UTC 2023
Allow user to configure the CCS mode setting through a
'ccs_mode' sysfs interface. Also report the current
CCS mode configuration and number of compute slices
available through this interface.
v2: Rebase, make it platform agnostic
Signed-off-by: Niranjana Vishwanathapura <niranjana.vishwanathapura at intel.com>
---
drivers/gpu/drm/xe/xe_gt.c | 6 +++
drivers/gpu/drm/xe/xe_gt_ccs_mode.c | 74 +++++++++++++++++++++++++++++
drivers/gpu/drm/xe/xe_gt_ccs_mode.h | 1 +
3 files changed, 81 insertions(+)
diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
index 1e534dd7e2a8..2622e6ea7f57 100644
--- a/drivers/gpu/drm/xe/xe_gt.c
+++ b/drivers/gpu/drm/xe/xe_gt.c
@@ -380,6 +380,12 @@ static int gt_fw_domain_init(struct xe_gt *gt)
"failed to register engines sysfs directory, err: %d\n",
err);
+ err = xe_gt_ccs_mode_sysfs_init(gt);
+ if (err)
+ drm_warn(>_to_xe(gt)->drm,
+ "Sysfs creation for ccs_mode setting failed err: %d\n",
+ err);
+
err = xe_force_wake_put(gt_to_fw(gt), XE_FW_GT);
XE_WARN_ON(err);
xe_device_mem_access_put(gt_to_xe(gt));
diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
index 8441316bb35c..0ad97383aedd 100644
--- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.c
@@ -3,10 +3,13 @@
* Copyright © 2023 Intel Corporation
*/
+#include <drm/drm_managed.h>
+
#include "regs/xe_gt_regs.h"
#include "xe_assert.h"
#include "xe_gt.h"
#include "xe_gt_ccs_mode.h"
+#include "xe_gt_sysfs.h"
#include "xe_mmio.h"
static void __xe_gt_apply_ccs_mode(struct xe_gt *gt, u32 num_engines)
@@ -71,3 +74,74 @@ void xe_gt_apply_ccs_mode(struct xe_gt *gt)
if (gt->ccs_mode.num_engines)
__xe_gt_apply_ccs_mode(gt, gt->ccs_mode.num_engines);
}
+
+static ssize_t
+ccs_mode_show(struct device *kdev,
+ struct device_attribute *attr, char *buf)
+{
+ struct xe_gt *gt = kobj_to_gt(&kdev->kobj);
+
+ return sysfs_emit(buf, "Enabled compute engines %d; Number of compute slices %d\n",
+ gt->ccs_mode.num_engines, hweight32(CCS_MASK(gt)));
+}
+
+static ssize_t
+ccs_mode_store(struct device *kdev, struct device_attribute *attr,
+ const char *buff, size_t count)
+{
+ struct xe_gt *gt = kobj_to_gt(&kdev->kobj);
+ u32 num_engines, num_slices;
+ int ret;
+
+ ret = kstrtou32(buff, 0, &num_engines);
+ if (ret)
+ return ret;
+
+ /*
+ * Ensure number of engines specified is valid and there is an
+ * exact multiple of engines for slices.
+ */
+ num_slices = hweight32(CCS_MASK(gt));
+ if (!num_engines || num_engines > num_slices || num_slices % num_engines) {
+ xe_gt_dbg(gt, "Invalid compute config, %d engines %d slices\n",
+ num_engines, num_slices);
+ return -EINVAL;
+ }
+
+ if (gt->ccs_mode.num_engines != num_engines) {
+ xe_gt_info(gt, "Setting compute mode to %d\n", num_engines);
+ gt->ccs_mode.num_engines = num_engines;
+ xe_gt_reset_async(gt);
+ }
+
+ return count;
+}
+
+static DEVICE_ATTR_RW(ccs_mode);
+
+static void xe_gt_ccs_mode_sysfs_fini(struct drm_device *drm, void *arg)
+{
+ struct xe_gt *gt = arg;
+
+ sysfs_remove_file(gt->sysfs, &dev_attr_ccs_mode.attr);
+}
+
+int xe_gt_ccs_mode_sysfs_init(struct xe_gt *gt)
+{
+ struct xe_device *xe = gt_to_xe(gt);
+ int err;
+
+ if (!xe_gt_ccs_mode_enabled(gt))
+ return 0;
+
+ err = sysfs_create_file(gt->sysfs, &dev_attr_ccs_mode.attr);
+ if (err)
+ return err;
+
+ err = drmm_add_action_or_reset(&xe->drm, xe_gt_ccs_mode_sysfs_fini, gt);
+ if (err)
+ drm_warn(&xe->drm, "%s: drmm_add_action_or_reset failed, err: %d\n",
+ __func__, err);
+
+ return err;
+}
diff --git a/drivers/gpu/drm/xe/xe_gt_ccs_mode.h b/drivers/gpu/drm/xe/xe_gt_ccs_mode.h
index 9aa6223ca83b..d09e2f9ae50a 100644
--- a/drivers/gpu/drm/xe/xe_gt_ccs_mode.h
+++ b/drivers/gpu/drm/xe/xe_gt_ccs_mode.h
@@ -12,6 +12,7 @@
#include "xe_platform_types.h"
void xe_gt_apply_ccs_mode(struct xe_gt *gt);
+int xe_gt_ccs_mode_sysfs_init(struct xe_gt *gt);
static inline bool xe_gt_ccs_mode_enabled(const struct xe_gt *gt)
{
--
2.21.0.rc0.32.g243a4c7e27
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