[Intel-xe] [PATCH v5 21/23] drm/xe/guc: Allocate GuC data structures in system memory for initial load
Matthew Brost
matthew.brost at intel.com
Wed Nov 29 18:13:04 UTC 2023
On Wed, Nov 29, 2023 at 11:35:06PM +0100, Michał Winiarski wrote:
> GuC load will need to happen at an earlier point in probe, where local
> memory is not yet available. Use system memory for GuC data structures
> used for initial "hwconfig" load, and realloc at a later,
> "post-hwconfig" load if needed, when local memory is available.
>
> Signed-off-by: Michał Winiarski <michal.winiarski at intel.com>
Reviewed-by: Matthew Brost <matthew.brost at intel.com>
> ---
> v3 -> v4:
> - Assert that realloc transisions from RAM to VRAM to make sure
> iosys_map API is used correctly (Lucas)
> - Fix GuC resource realloc by introducing drmm_release_action
>
> drivers/gpu/drm/xe/xe_bo.c | 5 +++
> drivers/gpu/drm/xe/xe_bo.h | 1 +
> drivers/gpu/drm/xe/xe_guc.c | 48 ++++++++++++++++++++++++++++
> drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_ct.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_hwconfig.c | 2 +-
> drivers/gpu/drm/xe/xe_guc_log.c | 2 +-
> 7 files changed, 58 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
> index 1a7fe62de8122..f8c744bd148c7 100644
> --- a/drivers/gpu/drm/xe/xe_bo.c
> +++ b/drivers/gpu/drm/xe/xe_bo.c
> @@ -1566,6 +1566,11 @@ struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_til
> return bo;
> }
>
> +void xe_managed_bo_release(struct xe_device *xe, struct xe_bo *bo)
> +{
> + drmm_release_action(&xe->drm, __xe_bo_release, bo);
> +}
> +
> /*
> * XXX: This is in the VM bind data path, likely should calculate this once and
> * store, with a recalculation if the BO is moved.
> diff --git a/drivers/gpu/drm/xe/xe_bo.h b/drivers/gpu/drm/xe/xe_bo.h
> index 098ccab7fa1e8..797d621075bd5 100644
> --- a/drivers/gpu/drm/xe/xe_bo.h
> +++ b/drivers/gpu/drm/xe/xe_bo.h
> @@ -119,6 +119,7 @@ struct xe_bo *xe_managed_bo_create_pin_map(struct xe_device *xe, struct xe_tile
> size_t size, u32 flags);
> struct xe_bo *xe_managed_bo_create_from_data(struct xe_device *xe, struct xe_tile *tile,
> const void *data, size_t size, u32 flags);
> +void xe_managed_bo_release(struct xe_device *xe, struct xe_bo *bo);
>
> int xe_bo_placement_for_flags(struct xe_device *xe, struct xe_bo *bo,
> u32 bo_flags);
> diff --git a/drivers/gpu/drm/xe/xe_guc.c b/drivers/gpu/drm/xe/xe_guc.c
> index 482cb0df9f15b..b85defa941e85 100644
> --- a/drivers/gpu/drm/xe/xe_guc.c
> +++ b/drivers/gpu/drm/xe/xe_guc.c
> @@ -241,6 +241,48 @@ static void guc_fini(struct drm_device *drm, void *arg)
> xe_force_wake_put(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL);
> }
>
> +static int __guc_bo_reinit(struct xe_guc *guc, struct xe_bo **src)
> +{
> + struct xe_tile *tile = gt_to_tile(guc_to_gt(guc));
> + struct xe_device *xe = guc_to_xe(guc);
> + struct xe_bo *bo;
> +
> + xe_assert(xe, !(*src)->vmap.is_iomem);
> +
> + bo = xe_managed_bo_create_from_data(xe, tile, &(*src)->vmap.vaddr, (*src)->size,
> + XE_BO_CREATE_VRAM_IF_DGFX(tile) |
> + XE_BO_CREATE_GGTT_BIT);
> + if (IS_ERR(bo))
> + return PTR_ERR(bo);
> +
> + xe_managed_bo_release(xe, *src);
> + *src = bo;
> +
> + return 0;
> +}
> +
> +static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc)
> +{
> + int ret;
> +
> + if (!IS_DGFX(guc_to_xe(guc)))
> + return 0;
> +
> + ret = __guc_bo_reinit(guc, &guc->log.bo);
> + if (ret)
> + return ret;
> +
> + ret = __guc_bo_reinit(guc, &guc->ads.bo);
> + if (ret)
> + return ret;
> +
> + ret = __guc_bo_reinit(guc, &guc->ct.bo);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> int xe_guc_init(struct xe_guc *guc)
> {
> struct xe_device *xe = guc_to_xe(guc);
> @@ -299,6 +341,12 @@ int xe_guc_init(struct xe_guc *guc)
> */
> int xe_guc_init_post_hwconfig(struct xe_guc *guc)
> {
> + int ret;
> +
> + ret = xe_guc_realloc_post_hwconfig(guc);
> + if (ret)
> + return ret;
> +
> guc_init_params_post_hwconfig(guc);
>
> return xe_guc_ads_init_post_hwconfig(&guc->ads);
> diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c
> index 2f5ff090aa6bd..61b443981f99a 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ads.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ads.c
> @@ -272,7 +272,7 @@ int xe_guc_ads_init(struct xe_guc_ads *ads)
> ads->regset_size = calculate_regset_size(gt);
>
> bo = xe_managed_bo_create_pin_map(xe, tile, guc_ads_size(ads) + MAX_GOLDEN_LRC_SIZE,
> - XE_BO_CREATE_VRAM_IF_DGFX(tile) |
> + XE_BO_CREATE_SYSTEM_BIT |
> XE_BO_CREATE_GGTT_BIT);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
> diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c
> index 24a33fa36496a..316e77362a825 100644
> --- a/drivers/gpu/drm/xe/xe_guc_ct.c
> +++ b/drivers/gpu/drm/xe/xe_guc_ct.c
> @@ -148,7 +148,7 @@ int xe_guc_ct_init(struct xe_guc_ct *ct)
> primelockdep(ct);
>
> bo = xe_managed_bo_create_pin_map(xe, tile, guc_ct_size(),
> - XE_BO_CREATE_VRAM_IF_DGFX(tile) |
> + XE_BO_CREATE_SYSTEM_BIT |
> XE_BO_CREATE_GGTT_BIT);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
> diff --git a/drivers/gpu/drm/xe/xe_guc_hwconfig.c b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
> index 2a13a00917f8c..ea49f3885c108 100644
> --- a/drivers/gpu/drm/xe/xe_guc_hwconfig.c
> +++ b/drivers/gpu/drm/xe/xe_guc_hwconfig.c
> @@ -78,7 +78,7 @@ int xe_guc_hwconfig_init(struct xe_guc *guc)
> return -EINVAL;
>
> bo = xe_managed_bo_create_pin_map(xe, tile, PAGE_ALIGN(size),
> - XE_BO_CREATE_VRAM_IF_DGFX(tile) |
> + XE_BO_CREATE_SYSTEM_BIT |
> XE_BO_CREATE_GGTT_BIT);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
> diff --git a/drivers/gpu/drm/xe/xe_guc_log.c b/drivers/gpu/drm/xe/xe_guc_log.c
> index bcd2f4d34081d..45135c3520e54 100644
> --- a/drivers/gpu/drm/xe/xe_guc_log.c
> +++ b/drivers/gpu/drm/xe/xe_guc_log.c
> @@ -84,7 +84,7 @@ int xe_guc_log_init(struct xe_guc_log *log)
> struct xe_bo *bo;
>
> bo = xe_managed_bo_create_pin_map(xe, tile, guc_log_size(),
> - XE_BO_CREATE_VRAM_IF_DGFX(tile) |
> + XE_BO_CREATE_SYSTEM_BIT |
> XE_BO_CREATE_GGTT_BIT);
> if (IS_ERR(bo))
> return PTR_ERR(bo);
> --
> 2.43.0
>
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