[Intel-xe] [PATCH] fixup! drm/xe/uapi: Add support for CPU caching mode

[Matthew Auld]

Add back the padding check. It was removed since we originally used the
other u16 for the coh_mode, but that was removed and never merged.

Testcase: igt at xe_create@create-invalid-mbz
Signed-off-by: Matthew Auld <matthew.auld at intel.com>
Cc: Pallavi Mishra <pallavi.mishra at intel.com>
Cc: Francois Dugast <francois.dugast at intel.com>
---
 drivers/gpu/drm/xe/xe_bo.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/xe/xe_bo.c b/drivers/gpu/drm/xe/xe_bo.c
index d59501ffc22a..7f012f4c2b2d 100644
--- a/drivers/gpu/drm/xe/xe_bo.c
+++ b/drivers/gpu/drm/xe/xe_bo.c
@@ -1840,7 +1840,7 @@ int xe_gem_create_ioctl(struct drm_device *dev, void *data,
 	u32 handle;
 	int err;
 
-	if (XE_IOCTL_DBG(xe, args->extensions) ||
+	if (XE_IOCTL_DBG(xe, args->extensions) || XE_IOCTL_DBG(xe, args->pad) ||
 	    XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1]))
 		return -EINVAL;
 
-- 
2.43.0