[Intel-xe] [PATCH] drm/xe: Leverage ComputeCS read L3 caching

[Lucas De Marchi]

On Fri, Sep 29, 2023 at 12:58:11PM -0700, Matt Roper wrote:
>On Thu, Sep 28, 2023 at 10:15:39PM -0700, Lucas De Marchi wrote:
>> From: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
>>
>> On platforms that support read L3 caching, set the default mocs index in
>> CCS RING_CMD_CTL to levarage the read caching in L3.
>>
>> Currently PVC and Xe2 platforms have the support.
>>
>> Bspec: 72161
>> Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan at intel.com>
>> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
>
>Reviewed-by: Matt Roper <matthew.d.roper at intel.com>

thanks, applied

Lucas De Marchi