[Intel-xe] [PATCH 3/3] drm/xe: Remove devcoredump readout of IPEIR

[Rodrigo Vivi]

On Wed, Oct 04, 2023 at 01:15:13PM -0400, Souza, Jose wrote:
> On Wed, 2023-10-04 at 13:11 -0400, Rodrigo Vivi wrote:
> > On Tue, Oct 03, 2023 at 01:27:28PM -0700, José Roberto de Souza wrote:
> > > This register don't exist in gfx12+, so here dropping the readout
> > > and print in devcoredump.
> > 
> > What about the RING_IPEIR ? also doesn't exist in newer platforms?
> 
> There is a chicken bit in 0x2064.

right, that seems indeed to only exist until gen11. A bug that is also
present in i915 btw.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>

> 
> > 
> > 
> > > 
> > > Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> > > ---
> > >  drivers/gpu/drm/xe/regs/xe_engine_regs.h | 2 --
> > >  drivers/gpu/drm/xe/xe_hw_engine.c        | 2 --
> > >  drivers/gpu/drm/xe/xe_hw_engine_types.h  | 2 --
> > >  3 files changed, 6 deletions(-)
> > > 
> > > diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > > index 792d431161c68..35dd4837dd75f 100644
> > > --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > > +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> > > @@ -31,12 +31,10 @@
> > >  
> > >  #define RING_ACTHD_UDW(base)			XE_REG((base) + 0x5c)
> > >  #define RING_DMA_FADD_UDW(base)			XE_REG((base) + 0x60)
> > > -#define RING_IPEIR(base)			XE_REG((base) + 0x64)
> > >  #define RING_IPEHR(base)			XE_REG((base) + 0x68)
> > >  #define RING_ACTHD(base)			XE_REG((base) + 0x74)
> > >  #define RING_DMA_FADD(base)			XE_REG((base) + 0x78)
> > >  #define RING_HWS_PGA(base)			XE_REG((base) + 0x80)
> > > -#define IPEIR(base)				XE_REG((base) + 0x88)
> > >  #define RING_HWSTAM(base)			XE_REG((base) + 0x98)
> > >  #define RING_MI_MODE(base)			XE_REG((base) + 0x9c)
> > >  #define RING_NOPID(base)			XE_REG((base) + 0x94)
> > > diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> > > index c2db391cf2674..f63c821baeb77 100644
> > > --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> > > +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> > > @@ -727,7 +727,6 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
> > >  		hw_engine_mmio_read32(hwe, RING_DMA_FADD_UDW(0));
> > >  	snapshot->reg.ring_dma_fadd =
> > >  		hw_engine_mmio_read32(hwe, RING_DMA_FADD(0));
> > > -	snapshot->reg.ipeir = hw_engine_mmio_read32(hwe, IPEIR(0));
> > >  	snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0));
> > >  
> > >  	if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
> > > @@ -784,7 +783,6 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
> > >  	drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> > >  		   snapshot->reg.ring_dma_fadd_udw,
> > >  		   snapshot->reg.ring_dma_fadd);
> > > -	drm_printf(p, "\tIPEIR: 0x%08x\n", snapshot->reg.ipeir);
> > >  	drm_printf(p, "\tIPEHR: 0x%08x\n\n", snapshot->reg.ipehr);
> > >  	if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
> > >  		drm_printf(p, "\tRCU_MODE: 0x%08x\n",
> > > diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> > > index cd4bc1412a3ff..5d4ee29042407 100644
> > > --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> > > +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> > > @@ -217,8 +217,6 @@ struct xe_hw_engine_snapshot {
> > >  		u32 ring_dma_fadd_udw;
> > >  		/** @ring_dma_fadd: RING_DMA_FADD */
> > >  		u32 ring_dma_fadd;
> > > -		/** @ipeir: IPEIR */
> > > -		u32 ipeir;
> > >  		/** @ipehr: IPEHR */
> > >  		u32 ipehr;
> > >  		/** @rcu_mode: RCU_MODE */
> > > -- 
> > > 2.42.0
> > > 
>