[Intel-xe] [PATCH 3/5] drm/xe/rpls: Add RPLS Support

[Lucas De Marchi]

On Tue, Oct 03, 2023 at 01:37:14PM -0700, Anusha Srivatsa wrote:
>Add RPLS support that was missing apart from the PCI IDs.
>
>v2: Also add the support in xe_wa_test kunit
>v3: rebased.
>
>Cc: Dnyaneshwar Bhadane <dnyaneshwar.bhadane at intel.com>
>Signed-off-by: Anusha Srivatsa <anusha.srivatsa at intel.com>
>Reviewed-by: Matt Roper <matthew.d.roper at intel.com>(v1)


Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>---
> drivers/gpu/drm/xe/tests/xe_wa_test.c  | 1 +
> drivers/gpu/drm/xe/xe_pci.c            | 7 +++++++
> drivers/gpu/drm/xe/xe_platform_types.h | 1 +
> 3 files changed, 9 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/tests/xe_wa_test.c b/drivers/gpu/drm/xe/tests/xe_wa_test.c
>index 16f7f157c875..69c9ea1fa82b 100644
>--- a/drivers/gpu/drm/xe/tests/xe_wa_test.c
>+++ b/drivers/gpu/drm/xe/tests/xe_wa_test.c
>@@ -49,6 +49,7 @@ static const struct platform_test_case cases[] = {
> 	PLATFORM_CASE(ALDERLAKE_P, A0),
> 	PLATFORM_CASE(ALDERLAKE_P, B0),
> 	PLATFORM_CASE(ALDERLAKE_P, C0),
>+	SUBPLATFORM_CASE(ALDERLAKE_S, RPLS, D0),
> 	SUBPLATFORM_CASE(DG2, G10, A0),
> 	SUBPLATFORM_CASE(DG2, G10, A1),
> 	SUBPLATFORM_CASE(DG2, G10, B0),
>diff --git a/drivers/gpu/drm/xe/xe_pci.c b/drivers/gpu/drm/xe/xe_pci.c
>index ba67f6fcfb4f..da485fb324eb 100644
>--- a/drivers/gpu/drm/xe/xe_pci.c
>+++ b/drivers/gpu/drm/xe/xe_pci.c
>@@ -221,6 +221,8 @@ static const struct xe_device_desc rkl_desc = {
> 	.require_force_probe = true,
> };
>
>+static const u16 adls_rpls_ids[] = { XE_RPLS_IDS(NOP), 0 };
>+
> static const struct xe_device_desc adl_s_desc = {
> 	.graphics = &graphics_xelp,
> 	.media = &media_xem,
>@@ -228,6 +230,10 @@ static const struct xe_device_desc adl_s_desc = {
> 	.has_display = true,
> 	.has_llc = true,
> 	.require_force_probe = true,
>+	.subplatforms = (const struct xe_subplatform_desc[]) {
>+		{ XE_SUBPLATFORM_ALDERLAKE_S_RPLS, "RPLS", adls_rpls_ids },
>+		{},
>+	},
> };
>
> static const u16 adlp_rplu_ids[] = { XE_RPLU_IDS(NOP), 0 };
>@@ -352,6 +358,7 @@ static const struct pci_device_id pciidlist[] = {
> 	XE_ADLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
> 	XE_ADLN_IDS(INTEL_VGA_DEVICE, &adl_n_desc),
> 	XE_RPLP_IDS(INTEL_VGA_DEVICE, &adl_p_desc),
>+	XE_RPLS_IDS(INTEL_VGA_DEVICE, &adl_s_desc),
> 	XE_DG1_IDS(INTEL_VGA_DEVICE, &dg1_desc),
> 	XE_ATS_M_IDS(INTEL_VGA_DEVICE, &ats_m_desc),
> 	XE_DG2_IDS(INTEL_VGA_DEVICE, &dg2_desc),
>diff --git a/drivers/gpu/drm/xe/xe_platform_types.h b/drivers/gpu/drm/xe/xe_platform_types.h
>index b6fe4342f9f6..553f53dbd093 100644
>--- a/drivers/gpu/drm/xe/xe_platform_types.h
>+++ b/drivers/gpu/drm/xe/xe_platform_types.h
>@@ -28,6 +28,7 @@ enum xe_subplatform {
> 	XE_SUBPLATFORM_UNINITIALIZED = 0,
> 	XE_SUBPLATFORM_NONE,
> 	XE_SUBPLATFORM_ALDERLAKE_P_RPLU,
>+	XE_SUBPLATFORM_ALDERLAKE_S_RPLS,
> 	XE_SUBPLATFORM_DG2_G10,
> 	XE_SUBPLATFORM_DG2_G11,
> 	XE_SUBPLATFORM_DG2_G12,
>-- 
>2.25.1
>