[Intel-xe] [PATCH v4 1/3] drm/xe/display: Add writing of remapped dpt

[Ruhl, Michael J]

>-----Original Message-----
>From: Intel-xe <intel-xe-bounces at lists.freedesktop.org> On Behalf Of Juha-
>Pekka Heikkila
>Sent: Friday, October 6, 2023 9:46 AM
>To: intel-xe at lists.freedesktop.org
>Subject: [Intel-xe] [PATCH v4 1/3] drm/xe/display: Add writing of remapped
>dpt
>
>Xe need to use remapped display page table for tiled framebuffers
>on anywhere else than DG2. Here add function to write such dpt
>
>Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
>---
> drivers/gpu/drm/xe/display/xe_fb_pin.c | 31
>++++++++++++++++++++++++++
> 1 file changed, 31 insertions(+)
>
>diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>index b7a04fba3585..8a1cb6c28eb0 100644
>--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>@@ -45,6 +45,37 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map
>*map, u32 *dpt_ofs, u32 bo_
> 	*dpt_ofs = ALIGN(*dpt_ofs, 4096);
> }
>
>+static void
>+write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32
>*dpt_ofs,
>+		   u32 bo_ofs, u32 width, u32 height, u32 src_stride,
>+		   u32 dst_stride)
>+{
>+	struct xe_device *xe = xe_bo_device(bo);
>+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
>+	u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset,
>+			     enum xe_cache_level cache) = ggtt->pt_ops-
>>pte_encode_bo;
>+	u32 column, row;
>+
>+	for (row = 0; row < height; row++) {
>+		u32 src_idx = src_stride * row + bo_ofs;
>+
>+		for (column = 0; column < width; column++) {
>+			iosys_map_wr(map, *dpt_ofs, u64,
>+				     pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
>+				     XE_CACHE_WB));
>+
>+			*dpt_ofs += 8;
>+			src_idx++;
>+		}
>+
>+		/* The DE ignores the PTEs for the padding tiles */
>+		*dpt_ofs += (dst_stride - width) * 8;
>+	}
>+
>+	/* Align to next page */
>+	*dpt_ofs = ALIGN(*dpt_ofs, 4096);

I know that this is mirroring the rotate code above, so the 4096 is "the same".

But  there is XE_PAGE_SIZE used in th iosys_map, and the alignment is set in patch 2
with XE_PAGE_SIZE.

Is the 4095 "ok", or should this be XE_PAGE_SIZE?

If it is ok:

Reviewed-by: Michael J. Ruhl <michael.j.ruhl at intel.com>

Otherwise, the r/b will be good after that update.

Thanks!

M

>+}
>+
> static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
> 			       const struct i915_gtt_view *view,
> 			       struct i915_vma *vma)
>--
>2.25.1