[Intel-xe] [PATCH] drm/xe: Add INSTDONE register to devcoredump
Rodrigo Vivi
rodrigo.vivi at intel.com
Fri Oct 6 19:23:31 UTC 2023
On Fri, Oct 06, 2023 at 12:19:39PM -0700, José Roberto de Souza wrote:
> This register contains important information that can help with debug
> of GPU hangs.
>
> While at it also fixing the double line jump at the end of engine
> registers for CCS engines.
indeed a very important missing piece. What about the other INSTDONE
variants?
anyway,
Reviewed-by: Rodrigo Vivi <rodrigo.vivi at intel.com>
>
> Cc: Lionel Landwerlin <lionel.g.landwerlin at intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_engine_regs.h | 1 +
> drivers/gpu/drm/xe/xe_hw_engine.c | 5 ++++-
> drivers/gpu/drm/xe/xe_hw_engine_types.h | 2 ++
> 3 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_engine_regs.h b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> index 35dd4837dd75f..32465e384fc24 100644
> --- a/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_engine_regs.h
> @@ -32,6 +32,7 @@
> #define RING_ACTHD_UDW(base) XE_REG((base) + 0x5c)
> #define RING_DMA_FADD_UDW(base) XE_REG((base) + 0x60)
> #define RING_IPEHR(base) XE_REG((base) + 0x68)
> +#define RING_INSTDONE(base) XE_REG((base) + 0x6c)
> #define RING_ACTHD(base) XE_REG((base) + 0x74)
> #define RING_DMA_FADD(base) XE_REG((base) + 0x78)
> #define RING_HWS_PGA(base) XE_REG((base) + 0x80)
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine.c b/drivers/gpu/drm/xe/xe_hw_engine.c
> index f63c821baeb77..52acfe1d8b6aa 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine.c
> +++ b/drivers/gpu/drm/xe/xe_hw_engine.c
> @@ -728,6 +728,7 @@ xe_hw_engine_snapshot_capture(struct xe_hw_engine *hwe)
> snapshot->reg.ring_dma_fadd =
> hw_engine_mmio_read32(hwe, RING_DMA_FADD(0));
> snapshot->reg.ipehr = hw_engine_mmio_read32(hwe, RING_IPEHR(0));
> + snapshot->reg.ring_instdone = hw_engine_mmio_read32(hwe, RING_INSTDONE(0));
>
> if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
> snapshot->reg.rcu_mode = xe_mmio_read32(hwe->gt, RCU_MODE);
> @@ -783,10 +784,12 @@ void xe_hw_engine_snapshot_print(struct xe_hw_engine_snapshot *snapshot,
> drm_printf(p, "\tDMA_FADDR: 0x%08x_%08x\n",
> snapshot->reg.ring_dma_fadd_udw,
> snapshot->reg.ring_dma_fadd);
> - drm_printf(p, "\tIPEHR: 0x%08x\n\n", snapshot->reg.ipehr);
> + drm_printf(p, "\tIPEHR: 0x%08x\n", snapshot->reg.ipehr);
> + drm_printf(p, "\tRING_INSTDONE: 0x%08x\n", snapshot->reg.ring_instdone);
> if (snapshot->class == XE_ENGINE_CLASS_COMPUTE)
> drm_printf(p, "\tRCU_MODE: 0x%08x\n",
> snapshot->reg.rcu_mode);
> + drm_puts(p, "\n");
> }
>
> /**
> diff --git a/drivers/gpu/drm/xe/xe_hw_engine_types.h b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> index 5d4ee29042407..dc164d51579bd 100644
> --- a/drivers/gpu/drm/xe/xe_hw_engine_types.h
> +++ b/drivers/gpu/drm/xe/xe_hw_engine_types.h
> @@ -221,6 +221,8 @@ struct xe_hw_engine_snapshot {
> u32 ipehr;
> /** @rcu_mode: RCU_MODE */
> u32 rcu_mode;
> + /** @ring_instdone: RING_INSTDONE */
> + u32 ring_instdone;
> } reg;
> };
>
> --
> 2.42.0
>
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