[Intel-xe] [PATCH v3] drm/xe: Set PTE_AE for smem allocations in integrated devices

[Matt Roper]

On Tue, Oct 10, 2023 at 01:02:56PM -0700, José Roberto de Souza wrote:
> Without this if a atomic operation is executed in Xe2 integrated GPUs
> it causes engine memory catastrophic error.

Technically it just causes a pagefault (which will be handled by the
driver rather than triggering a cat error once we turn on USM support),
right?  But since we're not handling page faults yet, this gets raised
as a cat error today.

Nevertheless, the fix here is correct; even with USM turned on we don't
want to be forcing pagefaults for igpu atomic operations on SMEM
addresses because the igpu can already perform those atomics properly.
Only on dgpu's like PVC do we need to trigger a migration from
smem->vram before letting the atomic operation go forward.

Reviewed-by: Matt Roper <matthew.d.roper at intel.com>


Matt

> 
> This fixes at least 3 failures in piglit sanity and 2 failures in
> crucible for LNL.
> 
> v3:
> - only add PTE_AE to smem in integrated
> 
> Cc: Matt Roper <matthew.d.roper at intel.com>
> Cc: Lucas De Marchi <lucas.demarchi at intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
> ---
>  drivers/gpu/drm/xe/xe_pt.c | 9 ++++++---
>  1 file changed, 6 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
> index f7553a2415acc..31afab617b4ed 100644
> --- a/drivers/gpu/drm/xe/xe_pt.c
> +++ b/drivers/gpu/drm/xe/xe_pt.c
> @@ -628,6 +628,7 @@ static int
>  xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
>  		 struct xe_vm_pgtable_update *entries, u32 *num_entries)
>  {
> +	struct xe_device *xe = tile_to_xe(tile);
>  	struct xe_bo *bo = xe_vma_bo(vma);
>  	bool is_devmem = !xe_vma_is_userptr(vma) && bo &&
>  		(xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo));
> @@ -649,10 +650,12 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
>  	struct xe_pt *pt = xe_vma_vm(vma)->pt_root[tile->id];
>  	int ret;
>  
> +	if (vma && (vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT) &&
> +	    (is_devmem || !IS_DGFX(xe)))
> +		xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
> +
>  	if (is_devmem) {
> -		xe_walk.default_pte = XE_PPGTT_PTE_DM;
> -		if (vma && vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT)
> -			xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
> +		xe_walk.default_pte |= XE_PPGTT_PTE_DM;
>  		xe_walk.dma_offset = vram_region_gpu_offset(bo->ttm.resource);
>  		xe_walk.cache = XE_CACHE_WB;
>  	} else {
> -- 
> 2.42.0
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation