[Intel-xe] [PATCH v3] drm/xe: Set PTE_AE for smem allocations in integrated devices

[Lucas De Marchi]

On Tue, Oct 10, 2023 at 01:02:56PM -0700, Jose Souza wrote:
>Without this if a atomic operation is executed in Xe2 integrated GPUs
>it causes engine memory catastrophic error.
>
>This fixes at least 3 failures in piglit sanity and 2 failures in
>crucible for LNL.
>
>v3:
>- only add PTE_AE to smem in integrated
>
>Cc: Matt Roper <matthew.d.roper at intel.com>
>Cc: Lucas De Marchi <lucas.demarchi at intel.com>
>Signed-off-by: José Roberto de Souza <jose.souza at intel.com>
>---
> drivers/gpu/drm/xe/xe_pt.c | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c
>index f7553a2415acc..31afab617b4ed 100644
>--- a/drivers/gpu/drm/xe/xe_pt.c
>+++ b/drivers/gpu/drm/xe/xe_pt.c
>@@ -628,6 +628,7 @@ static int
> xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
> 		 struct xe_vm_pgtable_update *entries, u32 *num_entries)
> {
>+	struct xe_device *xe = tile_to_xe(tile);
> 	struct xe_bo *bo = xe_vma_bo(vma);
> 	bool is_devmem = !xe_vma_is_userptr(vma) && bo &&
> 		(xe_bo_is_vram(bo) || xe_bo_is_stolen_devmem(bo));
>@@ -649,10 +650,12 @@ xe_pt_stage_bind(struct xe_tile *tile, struct xe_vma *vma,
> 	struct xe_pt *pt = xe_vma_vm(vma)->pt_root[tile->id];
> 	int ret;
>
>+	if (vma && (vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT) &&
>+	    (is_devmem || !IS_DGFX(xe)))
>+		xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;

it seems strange that we decide if the platform supports it in
xe_vma_create(), then decide if we should honour the flag only here.
Reading it I had the impression that it would start failing on e.g. TGL,
but then I saw that in xe_vma_create() it checks for the graphics
version. So... it does seem to cover all the corner cases.

Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>

Lucas De Marchi

>+
> 	if (is_devmem) {
>-		xe_walk.default_pte = XE_PPGTT_PTE_DM;
>-		if (vma && vma->gpuva.flags & XE_VMA_ATOMIC_PTE_BIT)
>-			xe_walk.default_pte |= XE_USM_PPGTT_PTE_AE;
>+		xe_walk.default_pte |= XE_PPGTT_PTE_DM;
> 		xe_walk.dma_offset = vram_region_gpu_offset(bo->ttm.resource);
> 		xe_walk.cache = XE_CACHE_WB;
> 	} else {
>-- 
>2.42.0
>