[Intel-xe] [PATCH 4/6] drm/xe: Extract MI_* instructions to their own header
Lucas De Marchi
lucas.demarchi at intel.com
Thu Oct 12 21:17:38 UTC 2023
On Wed, Oct 11, 2023 at 04:10:02PM -0700, Matt Roper wrote:
>Extracting the common MI_* instructions that can be used with any engine
>to their own header will make it easier as we add additional engine
>instructions in upcoming patches.
>
>Also, since the majority of GPU instructions (both MI and non-MI) have
>a "length" field in bits 7:0 of the instruction header, a common define
>is added for that. Instruction-specific length fields are still defined
>for special case instructions that have larger/smaller length fields.
>
>Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
>---
> .../gpu/drm/xe/instructions/xe_inst_defs.h | 31 ++++++++++
> .../gpu/drm/xe/instructions/xe_mi_commands.h | 58 +++++++++++++++++++
> drivers/gpu/drm/xe/regs/xe_gpu_commands.h | 41 -------------
> drivers/gpu/drm/xe/xe_bb.c | 1 +
> drivers/gpu/drm/xe/xe_execlist.c | 1 +
> drivers/gpu/drm/xe/xe_gt.c | 1 +
> drivers/gpu/drm/xe/xe_lrc.c | 1 +
> drivers/gpu/drm/xe/xe_migrate.c | 1 +
> drivers/gpu/drm/xe/xe_ring_ops.c | 3 +-
> 9 files changed, 96 insertions(+), 42 deletions(-)
> create mode 100644 drivers/gpu/drm/xe/instructions/xe_inst_defs.h
> create mode 100644 drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>
>diff --git a/drivers/gpu/drm/xe/instructions/xe_inst_defs.h b/drivers/gpu/drm/xe/instructions/xe_inst_defs.h
>new file mode 100644
>index 000000000000..c992ad767f08
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/instructions/xe_inst_defs.h
>@@ -0,0 +1,31 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2023 Intel Corporation
>+ */
>+
>+#ifndef _XE_INST_DEFS_H_
>+#define _XE_INST_DEFS_H_
>+
>+#include "compat-i915-headers/i915_reg_defs.h"
I think we want this to be xe/xe_reg_defs.h. Eventually I want to get
rid of the i915 dependency... I have a patch series for that from a few
months ago that I need to follow up on.
>+
>+/*
>+ * The first dword of any GPU instruction is the "instruction header." Bits
>+ * 31:29 identify the general type of the command and determine how exact
>+ * opcodes and sub-opcodes will be encoded in the remaining bits.
>+ */
>+#define XE_INST_CMD_TYPE GENMASK(31, 29)
>+#define XE_INST_MI REG_FIELD_PREP(XE_INST_CMD_TYPE, 0x0)
maybe because I got used to MI_INSTR(), but I think instr is a better
short name for "instruction"
>+
>+/*
>+ * Most (but not all) instructions have a "length" field in the instruction
>+ * header. The value expected is the total number of dwords for the
>+ * instruction, minus two.
>+ *
>+ * Some instructions have length fields longer or shorter than 8 bits, but
>+ * those are rare. This definition can be used for the common case where
>+ * the length field is from 7:0.
>+ */
>+#define XE_INST_LEN_MASK GENMASK(7, 0)
>+#define XE_INST_NUM_DW(x) REG_FIELD_PREP(XE_INST_LEN_MASK, (x) - 2)
>+
>+#endif
>diff --git a/drivers/gpu/drm/xe/instructions/xe_mi_commands.h b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>new file mode 100644
>index 000000000000..4a37b2b86b40
>--- /dev/null
>+++ b/drivers/gpu/drm/xe/instructions/xe_mi_commands.h
>@@ -0,0 +1,58 @@
>+/* SPDX-License-Identifier: MIT */
>+/*
>+ * Copyright © 2023 Intel Corporation
>+ */
>+
>+#ifndef _XE_MI_COMMANDS_H_
>+#define _XE_MI_COMMANDS_H_
>+
>+#include "instructions/xe_inst_defs.h"
>+
>+/*
>+ * MI (Memory Interface) commands are supported by all GT engines. They
>+ * provide general memory operations and command streamer control. MI commands
>+ * have a command type of 0x0 (MI_COMMAND) in bits 31:29 of the instruction
>+ * header dword and a specific MI opcode in bits 28:23.
>+ */
>+
>+#define MI_OPCODE REG_GENMASK(28, 23)
>+#define MI_SUBOPCODE REG_GENMASK(22, 17) /* used with MI_EXPANSION */
>+
>+#define __MI_INST(opcode) \
>+ (XE_INST_MI | REG_FIELD_PREP(MI_OPCODE, opcode))
>+
>+#define MI_NOOP __MI_INST(0x0)
>+#define MI_USER_INTERRUPT __MI_INST(0x2)
>+#define MI_ARB_CHECK __MI_INST(0x5)
>+
>+#define MI_ARB_ON_OFF __MI_INST(0x8)
>+#define MI_ARB_ENABLE REG_BIT(0)
>+#define MI_ARB_DISABLE 0x0
>+
>+#define MI_BATCH_BUFFER_END __MI_INST(0xA)
>+#define MI_STORE_DATA_IMM __MI_INST(0x20)
>+#define MI_SDI_GGTT REG_BIT(22)
>+#define MI_SDI_LEN_DW GENMASK(9, 0)
>+#define MI_SDI_NUM_DW(x) REG_FIELD_PREP(MI_SDI_LEN_DW, (x) + 3 - 2)
>+#define MI_SDI_NUM_QW(x) (REG_FIELD_PREP(MI_SDI_LEN_DW, 2 * (x) + 3 - 2) | \
>+ REG_BIT(21))
>+
>+#define MI_LOAD_REGISTER_IMM __MI_INST(0x22)
>+#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
>+#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
>+#define MI_LRI_NUM_REGS(x) XE_INST_NUM_DW(2 * (x) + 1)
>+#define MI_LRI_FORCE_POSTED REG_BIT(12)
>+
>+#define MI_FLUSH_DW __MI_INST(0x26)
>+#define MI_FLUSH_DW_STORE_INDEX REG_BIT(21)
>+#define MI_INVALIDATE_TLB REG_BIT(18)
>+#define MI_FLUSH_DW_CCS REG_BIT(16)
>+#define MI_FLUSH_DW_OP_STOREDW REG_BIT(14)
>+#define MI_FLUSH_DW_LEN_DW REG_GENMASK(5, 0)
>+#define MI_FLUSH_IMM_DW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 4 - 2)
>+#define MI_FLUSH_IMM_QW REG_FIELD_PREP(MI_FLUSH_DW_LEN_DW, 5 - 2)
>+#define MI_FLUSH_DW_USE_GTT REG_BIT(2)
>+
>+#define MI_BATCH_BUFFER_START __MI_INST(0x31)
>+
>+#endif
>diff --git a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
>index 8c2e0da694d8..4402f72481dc 100644
>--- a/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
>+++ b/drivers/gpu/drm/xe/regs/xe_gpu_commands.h
>@@ -8,45 +8,6 @@
>
> #include "regs/xe_reg_defs.h"
>
>-#define INSTR_CLIENT_SHIFT 29
>-#define INSTR_MI_CLIENT 0x0
>-#define __INSTR(client) ((client) << INSTR_CLIENT_SHIFT)
>-
>-#define MI_INSTR(opcode, flags) \
>- (__INSTR(INSTR_MI_CLIENT) | (opcode) << 23 | (flags))
>-
>-#define MI_NOOP MI_INSTR(0, 0)
>-#define MI_USER_INTERRUPT MI_INSTR(0x02, 0)
>-
>-#define MI_ARB_ON_OFF MI_INSTR(0x08, 0)
>-#define MI_ARB_ENABLE (1<<0)
>-#define MI_ARB_DISABLE (0<<0)
>-
>-#define MI_BATCH_BUFFER_END MI_INSTR(0x0a, 0)
>-#define MI_STORE_DATA_IMM MI_INSTR(0x20, 0)
>-#define MI_SDI_GGTT REG_BIT(22)
>-#define MI_SDI_NUM_DW(x) ((x) + 1)
>-#define MI_SDI_NUM_QW(x) (REG_BIT(21) | (2 * (x) + 1))
>-
>-#define MI_LOAD_REGISTER_IMM MI_INSTR(0x22, 0)
>-#define MI_LRI_LRM_CS_MMIO REG_BIT(19)
>-#define MI_LRI_MMIO_REMAP_EN REG_BIT(17)
>-#define MI_LRI_LENGTH GENMASK(5, 0)
>-#define MI_LRI_NUM_REGS(x) REG_FIELD_PREP(MI_LRI_LENGTH, 2 * (x) - 1)
>-#define MI_LRI_FORCE_POSTED (1<<12)
>-
>-#define MI_FLUSH_DW MI_INSTR(0x26, 0)
>-#define MI_FLUSH_DW_STORE_INDEX (1<<21)
>-#define MI_INVALIDATE_TLB (1<<18)
>-#define MI_FLUSH_DW_CCS (1<<16)
>-#define MI_FLUSH_DW_OP_STOREDW (1<<14)
>-#define MI_FLUSH_DW_USE_GTT (1<<2)
>-#define MI_FLUSH_LENGTH GENMASK(5, 0)
>-#define MI_FLUSH_IMM_DW REG_FIELD_PREP(MI_FLUSH_LENGTH, 2)
>-#define MI_FLUSH_IMM_QW REG_FIELD_PREP(MI_FLUSH_LENGTH, 3)
>-
>-#define MI_BATCH_BUFFER_START MI_INSTR(0x31, 1)
>-
> #define XY_CTRL_SURF_COPY_BLT ((2 << 29) | (0x48 << 22) | 3)
are you planning to finish the move of other instructions out of
xe/regs? It doesn't need to be in this patch, but it'd be better to have
a follow up patch with the move.
Lucas De Marchi
> #define SRC_ACCESS_TYPE_SHIFT 21
> #define DST_ACCESS_TYPE_SHIFT 20
>@@ -106,6 +67,4 @@
> #define PIPE_CONTROL_STALL_AT_SCOREBOARD (1<<1)
> #define PIPE_CONTROL_DEPTH_CACHE_FLUSH (1<<0)
>
>-#define MI_ARB_CHECK MI_INSTR(0x05, 0)
>-
> #endif
>diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c
>index f871ba82bc9b..7c124475c428 100644
>--- a/drivers/gpu/drm/xe/xe_bb.c
>+++ b/drivers/gpu/drm/xe/xe_bb.c
>@@ -5,6 +5,7 @@
>
> #include "xe_bb.h"
>
>+#include "instructions/xe_mi_commands.h"
> #include "regs/xe_gpu_commands.h"
> #include "xe_device.h"
> #include "xe_exec_queue_types.h"
>diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c
>index 5be7f53f023a..811b81c39002 100644
>--- a/drivers/gpu/drm/xe/xe_execlist.c
>+++ b/drivers/gpu/drm/xe/xe_execlist.c
>@@ -7,6 +7,7 @@
>
> #include <drm/drm_managed.h>
>
>+#include "instructions/xe_mi_commands.h"
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
>diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c
>index a42ee3b9b8c7..74e1f47bd401 100644
>--- a/drivers/gpu/drm/xe/xe_gt.c
>+++ b/drivers/gpu/drm/xe/xe_gt.c
>@@ -10,6 +10,7 @@
> #include <drm/drm_managed.h>
> #include <drm/xe_drm.h>
>
>+#include "instructions/xe_mi_commands.h"
> #include "regs/xe_gt_regs.h"
> #include "xe_assert.h"
> #include "xe_bb.h"
>diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c
>index 81463bd5e490..a04867131839 100644
>--- a/drivers/gpu/drm/xe/xe_lrc.c
>+++ b/drivers/gpu/drm/xe/xe_lrc.c
>@@ -5,6 +5,7 @@
>
> #include "xe_lrc.h"
>
>+#include "instructions/xe_mi_commands.h"
> #include "regs/xe_engine_regs.h"
> #include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
>diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c
>index 716f72ba8cd6..b4baecde60e6 100644
>--- a/drivers/gpu/drm/xe/xe_migrate.c
>+++ b/drivers/gpu/drm/xe/xe_migrate.c
>@@ -13,6 +13,7 @@
> #include <drm/xe_drm.h>
>
> #include "generated/xe_wa_oob.h"
>+#include "instructions/xe_mi_commands.h"
> #include "regs/xe_gpu_commands.h"
> #include "tests/xe_test.h"
> #include "xe_assert.h"
>diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c
>index da13cc7ba6af..26936c76a479 100644
>--- a/drivers/gpu/drm/xe/xe_ring_ops.c
>+++ b/drivers/gpu/drm/xe/xe_ring_ops.c
>@@ -6,6 +6,7 @@
> #include "xe_ring_ops.h"
>
> #include "generated/xe_wa_oob.h"
>+#include "instructions/xe_mi_commands.h"
> #include "regs/xe_gpu_commands.h"
> #include "regs/xe_gt_regs.h"
> #include "regs/xe_lrc_layout.h"
>@@ -91,7 +92,7 @@ static int emit_flush_imm_ggtt(u32 addr, u32 value, bool invalidate_tlb,
>
> static int emit_bb_start(u64 batch_addr, u32 ppgtt_flag, u32 *dw, int i)
> {
>- dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag;
>+ dw[i++] = MI_BATCH_BUFFER_START | ppgtt_flag | XE_INST_NUM_DW(3);
> dw[i++] = lower_32_bits(batch_addr);
> dw[i++] = upper_32_bits(batch_addr);
>
>--
>2.41.0
>
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