[Intel-xe] [PATCH v6 2/2] drm/xe/display: Add writing of remapped dpt

[Ruhl, Michael J]

>-----Original Message-----
>From: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
>Sent: Monday, October 16, 2023 10:54 AM
>To: Ruhl, Michael J <michael.j.ruhl at intel.com>
>Subject: Fwd: [PATCH v6 2/2] drm/xe/display: Add writing of remapped dpt
>
>Xe need to use remapped display page table for tiled framebuffers
>on anywhere else than DG2. Here add function to write such dpt and
>enable usage of remapped display page tables where needed.
>
>Signed-off-by: Juha-Pekka Heikkila <juhapekka.heikkila at gmail.com>
>---
>  drivers/gpu/drm/xe/display/xe_fb_pin.c | 52 +++++++++++++++++++++++--
>-
>  1 file changed, 46 insertions(+), 6 deletions(-)
>
>diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>index 89cf65c58191..ffd35a59f405 100644
>--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
>+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
>@@ -45,6 +45,37 @@ write_dpt_rotated(struct xe_bo *bo, struct iosys_map
>*map, u32 *dpt_ofs, u32 bo_
>  	*dpt_ofs = ALIGN(*dpt_ofs, 4096);
>  }
>  +static void
>+write_dpt_remapped(struct xe_bo *bo, struct iosys_map *map, u32
>*dpt_ofs,
>+		   u32 bo_ofs, u32 width, u32 height, u32 src_stride,
>+		   u32 dst_stride)
>+{
>+	struct xe_device *xe = xe_bo_device(bo);
>+	struct xe_ggtt *ggtt = xe_device_get_root_tile(xe)->mem.ggtt;
>+	u64 (*pte_encode_bo)(struct xe_bo *bo, u64 bo_offset, u16
>pat_index)
>+		= ggtt->pt_ops->pte_encode_bo;
>+	u32 column, row;
>+
>+	for (row = 0; row < height; row++) {
>+		u32 src_idx = src_stride * row + bo_ofs;
>+
>+		for (column = 0; column < width; column++) {
>+			iosys_map_wr(map, *dpt_ofs, u64,
>+				     pte_encode_bo(bo, src_idx * XE_PAGE_SIZE,
>+				     xe->pat.idx[XE_CACHE_WB]));
>+
>+			*dpt_ofs += 8;
>+			src_idx++;
>+		}
>+
>+		/* The DE ignores the PTEs for the padding tiles */
>+		*dpt_ofs += (dst_stride - width) * 8;
>+	}
>+
>+	/* Align to next page */
>+	*dpt_ofs = ALIGN(*dpt_ofs, 4096);

The use of 4096 here is unclear.

Should this value be XE_PAGE_SIZE?

If not, or updated with this value,

Reviewed-by: Michael J. Ruhl <michael.j.ruhl at intel.com>


>+}
>+
>  static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
>  			       const struct i915_gtt_view *view,
>  			       struct i915_vma *vma)
>@@ -57,6 +88,9 @@ static int __xe_pin_fb_vma_dpt(struct
>intel_framebuffer *fb,
>   	if (view->type == I915_GTT_VIEW_NORMAL)
>  		dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE);
>+	else if (view->type == I915_GTT_VIEW_REMAPPED)
>+		dpt_size =
>ALIGN(intel_remapped_info_size(&fb->remapped_view.gtt.remapped) * 8,
>+				 XE_PAGE_SIZE);
>  	else
>  		/* display uses 4K tiles instead of bytes here, convert to
>entries.. */
>  		dpt_size = ALIGN(intel_rotation_info_size(&view->rotated) * 8,
>@@ -89,6 +123,18 @@ static int __xe_pin_fb_vma_dpt(struct
>intel_framebuffer *fb,
>   			iosys_map_wr(&dpt->vmap, x * 8, u64, pte);
>  		}
>+	} else if (view->type == I915_GTT_VIEW_REMAPPED) {
>+		const struct intel_remapped_info *remap_info = &view-
>>remapped;
>+		u32 i, dpt_ofs = 0;
>+
>+		for (i = 0; i < ARRAY_SIZE(remap_info->plane); i++)
>+			write_dpt_remapped(bo, &dpt->vmap, &dpt_ofs,
>+					   remap_info->plane[i].offset,
>+					   remap_info->plane[i].width,
>+					   remap_info->plane[i].height,
>+					   remap_info->plane[i].src_stride,
>+					   remap_info->plane[i].dst_stride);
>+
>  	} else {
>  		const struct intel_rotation_info *rot_info = &view->rotated;
>  		u32 i, dpt_ofs = 0;
>@@ -212,12 +258,6 @@ static struct i915_vma *__xe_pin_fb_vma(struct
>intel_framebuffer *fb,
>  	if (!vma)
>  		return ERR_PTR(-ENODEV);
>  -	/* Remapped view is only required on ADL-P, which xe doesn't support.
>*/
>-	if (XE_WARN_ON(view->type == I915_GTT_VIEW_REMAPPED)) {
>-		ret = -ENODEV;
>-		goto err;
>-	}
>-
>  	if (IS_DGFX(to_xe_device(bo->ttm.base.dev)) &&
>  	    intel_fb_rc_ccs_cc_plane(&fb->base) >= 0 &&
>  	    !(bo->flags & XE_BO_NEEDS_CPU_ACCESS)) {
>--
>2.25.1