[Intel-xe] [PATCH v2 4/6] drm/xe: Extract MI_* instructions to their own header

[Matt Roper]

On Mon, Oct 16, 2023 at 10:57:07AM -0500, Lucas De Marchi wrote:
> On Fri, Oct 13, 2023 at 03:02:55PM -0700, Matt Roper wrote:
> > Extracting the common MI_* instructions that can be used with any engine
> > to their own header will make it easier as we add additional engine
> > instructions in upcoming patches.
> > 
> > Also, since the majority of GPU instructions (both MI and non-MI) have
> > a "length" field in bits 7:0 of the instruction header, a common define
> > is added for that.  Instruction-specific length fields are still defined
> > for special case instructions that have larger/smaller length fields.
> > 
> > v2:
> > - Use "instr" instead of "inst" as the short form of "instruction"
> >   everywhere.  (Lucas)
> > - Include xe_reg_defs.h instead of the i915 compat header.  (Lucas)
> > 
> > Signed-off-by: Matt Roper <matthew.d.roper at intel.com>
> > ---
> > .../gpu/drm/xe/instructions/xe_instr_defs.h   | 31 ++++++++++
> > .../gpu/drm/xe/instructions/xe_mi_commands.h  | 58 +++++++++++++++++++
> > drivers/gpu/drm/xe/regs/xe_gpu_commands.h     | 41 -------------
> > drivers/gpu/drm/xe/xe_bb.c                    |  1 +
> > drivers/gpu/drm/xe/xe_execlist.c              |  1 +
> > drivers/gpu/drm/xe/xe_gt.c                    |  1 +
> > drivers/gpu/drm/xe/xe_lrc.c                   |  1 +
> > drivers/gpu/drm/xe/xe_migrate.c               |  1 +
> > drivers/gpu/drm/xe/xe_ring_ops.c              |  3 +-
> > 9 files changed, 96 insertions(+), 42 deletions(-)
> > create mode 100644 drivers/gpu/drm/xe/instructions/xe_instr_defs.h
> > create mode 100644 drivers/gpu/drm/xe/instructions/xe_mi_commands.h
> > 
> > diff --git a/drivers/gpu/drm/xe/instructions/xe_instr_defs.h b/drivers/gpu/drm/xe/instructions/xe_instr_defs.h
> > new file mode 100644
> > index 000000000000..a7ec46395786
> > --- /dev/null
> > +++ b/drivers/gpu/drm/xe/instructions/xe_instr_defs.h
> > @@ -0,0 +1,31 @@
> > +/* SPDX-License-Identifier: MIT */
> > +/*
> > + * Copyright © 2023 Intel Corporation
> > + */
> > +
> > +#ifndef _XE_INSTR_DEFS_H_
> > +#define _XE_INSTR_DEFS_H_
> > +
> > +#include "regs/xe_reg_defs.h"
> > +
> > +/*
> > + * The first dword of any GPU instruction is the "instruction header."  Bits
> > + * 31:29 identify the general type of the command and determine how exact
> > + * opcodes and sub-opcodes will be encoded in the remaining bits.
> > + */
> > +#define XE_INSTR_CMD_TYPE		GENMASK(31, 29)
> > +#define   XE_INSTR_MI			REG_FIELD_PREP(XE_INSTR_CMD_TYPE, 0x0)
> > +
> > +/*
> > + * Most (but not all) instructions have a "length" field in the instruction
> > + * header.  The value expected is the total number of dwords for the
> > + * instruction, minus two.
> > + *
> > + * Some instructions have length fields longer or shorter than 8 bits, but
> > + * those are rare.  This definition can be used for the common case where
> > + * the length field is from 7:0.
> > + */
> > +#define XE_INSTR_LEN_MASK		GENMASK(7, 0)
> 
> nit: if this is not to be used outside this header, I guess it could use
> double underscore like you did for __MI_INSTR().

It does wind up getting used in instr_dw() in the next patch, so
probably best to leave it as-is for now.


Matt

> 
> Reviewed-by: Lucas De Marchi <lucas.demarchi at intel.com>
> 
> thanks
> Lucas De Marchi

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation