[Intel-xe] [PATCH 2/3] drm/xe: Add performance tuning settings for MTL and Xe2

[Matt Roper]

On Mon, Oct 23, 2023 at 08:21:37AM -0700, Lucas De Marchi wrote:
> From: Shekhar Chauhan <shekhar.chauhan at intel.com>
> 
> Adding L3SQCREG5 as part of HW recommended settings.
> Note: Programming exactly the values requested in the BSpec,
> even though the upper bits of the L3SQCREG5 register no longer
> exist on Xe2's primary GT, so the hardware will ignore them.

This description is slightly confusing; we're not actually writing the
high bits in the tuning setting below.  The bspec just gives a literal
value for the register tuning:

        L3SQCREG5:  00e0007f

On the primary GT's copy of the register bits 21-23 no longer exist in
Xe2_LPG, so the suggestion to set them is non-sense (Shekhar confirmed
offline with the hardware people that the recommendation is just a
copy/paste from MTL where those bits do exist, and setting them on Xe2
won't actually do anything).  The bits do still exist on the media GT,
but the hardware defaults are already set, so we don't need to set them
explicitly as a tuning setting.  The only bits that we need to adjust
from their default settings are 9:0 (hardware default is 0x1FF, the
suggested tuning setting is 0x7f).

There are a few other quirks to this tuning setting that might be worth
noting in the commit message as well:
 * On MTL, this register only existed on the primary GT, so the Xe_LPG
   version of the tuning doesn't have a media equivalent.
 * On MTL, the register was part of the RCS engine's context, which is
   why it's an LRC setting there.  It is no longer part of the context
   on Xe2, which is why it switches to a GT tuning.
 * Unlike most registers, which have the same relative offset on both
   the primary and media GT, this register has a different base offset
   on the media GT.


The actual implementation here looks correct, but you might want to
incorporate some/all of the information above into the commit message
for clarity.  Aside from that,

        Reviewed-by: Matt Roper <matthew.d.roper at intel.com>


Matt

> 
> Bspec: 72161
> Signed-off-by: Shekhar Chauhan <shekhar.chauhan at intel.com>
> Signed-off-by: Lucas De Marchi <lucas.demarchi at intel.com>
> ---
>  drivers/gpu/drm/xe/regs/xe_gt_regs.h |  2 ++
>  drivers/gpu/drm/xe/xe_tuning.c       | 23 +++++++++++++++++++++++
>  2 files changed, 25 insertions(+)
> 
> diff --git a/drivers/gpu/drm/xe/regs/xe_gt_regs.h b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> index 8e01ae49ef21..ec9d11b57bef 100644
> --- a/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_gt_regs.h
> @@ -292,6 +292,8 @@
>  
>  #define XEHPC_L3CLOS_MASK(i)			XE_REG_MCR(0xb194 + (i) * 8)
>  
> +#define XE2LPM_L3SQCREG5			XE_REG_MCR(0xb658)
> +
>  #define XEHP_MERT_MOD_CTRL			XE_REG_MCR(0xcf28)
>  #define RENDER_MOD_CTRL				XE_REG_MCR(0xcf2c)
>  #define COMP_MOD_CTRL				XE_REG_MCR(0xcf30)
> diff --git a/drivers/gpu/drm/xe/xe_tuning.c b/drivers/gpu/drm/xe/xe_tuning.c
> index d70519816522..53ccd338fd8c 100644
> --- a/drivers/gpu/drm/xe/xe_tuning.c
> +++ b/drivers/gpu/drm/xe/xe_tuning.c
> @@ -24,6 +24,20 @@ static const struct xe_rtp_entry_sr gt_tunings[] = {
>  	  XE_RTP_RULES(PLATFORM(DG2)),
>  	  XE_RTP_ACTIONS(SET(XEHP_SQCM, EN_32B_ACCESS))
>  	},
> +
> +	/* Xe2 */
> +
> +	{ XE_RTP_NAME("Tuning: L3 cache"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION(2004)),
> +	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> +				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
> +	},
> +	{ XE_RTP_NAME("Tuning: L3 cache - media"),
> +	  XE_RTP_RULES(MEDIA_VERSION(2000)),
> +	  XE_RTP_ACTIONS(FIELD_SET(XE2LPM_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> +				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
> +	},
> +
>  	{}
>  };
>  
> @@ -63,6 +77,15 @@ static const struct xe_rtp_entry_sr lrc_tunings[] = {
>  	  XE_RTP_RULES(PLATFORM(DG2), ENGINE_CLASS(RENDER)),
>  	  XE_RTP_ACTIONS(SET(CHICKEN_RASTER_2, TBIMR_FAST_CLIP))
>  	},
> +
> +	/* Xe_LPG */
> +
> +	{ XE_RTP_NAME("Tuning: L3 cache"),
> +	  XE_RTP_RULES(GRAPHICS_VERSION_RANGE(1270, 1271), ENGINE_CLASS(RENDER)),
> +	  XE_RTP_ACTIONS(FIELD_SET(XEHP_L3SQCREG5, L3_PWM_TIMER_INIT_VAL_MASK,
> +				   REG_FIELD_PREP(L3_PWM_TIMER_INIT_VAL_MASK, 0x7f)))
> +	},
> +
>  	{}
>  };
>  
> -- 
> 2.40.1
> 
> 

-- 
Matt Roper
Graphics Software Engineer
Linux GPU Platform Enablement
Intel Corporation